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4KW LLC教程教学数字开关电源、 LLC设计步骤 、关键元器件计算书、全过程就是逐步指导 变压器详细设计资料 原理图和pcblayout
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//###########################################################################
//
// FILE: Example_2803xAdcSoc.c
//
// TITLE: ADC Start of Conversion example
//
//! \addtogroup f2803x_example_list
//! <h1> ADC Start of Conversion (adc_soc)</h1>
//!
//! This ADC example uses ePWM1 to generate a periodic ADC SOC - ADCINT1.
//! Two channels are converted, ADCINA4 and ADCINA2.
//!
//! \b Watch \b Variables \n
//! - Voltage1[10] - Last 10 ADCRESULT0 values
//! - Voltage2[10] - Last 10 ADCRESULT1 values
//! - ConversionCount - Current result number 0-9
//! - LoopCount - Idle loop counter
//
//
//###########################################################################
// $TI Release: F2803x Support Library v2.01.00.00 $
// $Release Date: Mon May 22 15:41:40 CDT 2017 $
// $Copyright:
// Copyright (C) 2009-2017 Texas Instruments Incorporated - wwwticom
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//
// Included Files
//
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "ISR_50kHz.h"
#include <string.h>
#include <stdint.h>
//
// Function Prototypes
//
__interrupt void adc_isr(void);
void Adc_Config(void);
void EPWM1and2_Init(void);//LLC driver may be used in interleaving LLC
void EPWM3_Init(void);//50kHz AD_ISR triggle
void EPWM4_Init(void);//50kHz AD_ISR triggle
void EPWM5_Init(void);//DAC0 and DAC1
void ADC_Init(void);//ADC init
void GPIO_Init(void);
Uint16 LoopCount;
Uint16 ConversionCount;
Uint16 Voltage1[10];
Uint16 Voltage2[10];
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 RamfuncsRunStart;
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
{
while(SourceAddr < SourceEndAddr)
{
*DestAddr++ = *SourceAddr++;
}
return;
}
//
// Main
//
void main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
EALLOW;
InitPieVectTable();
EDIS;
EALLOW; // This is needed to write to EALLOW protected register
PieVectTable.EPWM4_INT = &adc_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
memcpy((uint16_t *)&RamfuncsRunStart,(uint16_t *)&RamfuncsLoadStart,
(unsigned long)&RamfuncsLoadSize);
GPIO_Init();
InitFlash();
InitSciGpio();
InitAdc(); // For this example, init the ADC
AdcOffsetSelfCal();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // enable TBCLK within the ePWM
EDIS;
IER |= M_INT3; // Enable CPU Interrupt 1
IER |= M_INT9; // Enable CPU Interrupt 9
// PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE
PieCtrlRegs.PIEIER3.bit.INTx4 = 1;//enable EPWM4 INterrput
PieCtrlRegs.PIEIER9.bit.INTx1=1;// Enable INT 9.1 in the PIE SCIRX interrupt
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
EPWM1and2_Init();
EPWM3_Init();
EPWM4_Init();
EPWM5_Init();
ADC_Init();
ID2DCalValueInit();
ID2DTime100us.TimebaseDebug1minCnt=0;
ID2DTime100us.TimebaseStateMachine5msCnt=0;
for(;;)
{
if(ISR_10KHzCnt>=4)
{
ISR_10KHzCnt=0;
ISR_10kHz();
}
}
}
void EPWM1and2_Init(void)
{
EALLOW;
// EPWM Module 1 config
EPwm1Regs.TBPRD = 600; // Period = 300 TBCLK counts 60M/100k=600
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // Sync down-stream module
EPwm1Regs.TBCTL.bit.CLKDIV=TB_DIV1;
EPwm1Regs.TBCTL.bit.HSPCLKDIV=TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module DBA_ALL
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBFED = 270; // FED = 270 TBCLKs
EPwm1Regs.DBRED = 270; // RED = 270 TBCLKs
// EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
// EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // Select SOC from from zero on upcount
// EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.TZSEL.bit.OSHT1=1;//TZ1 will be one shot signal for EPWM1
EPwm2Regs.TZSEL.bit.OSHT1=1;//TZ1 will be one shot signal for EPWM2
EPwm1Regs.TZSEL.bit.OSHT2=1;//TZ2 will be one shot signal for EPWM1
EPwm2Regs.TZSEL.bit.OSHT2=1;//TZ2 will be one shot signal for EPWM2
EPwm1Regs.TZSEL.bit.OSHT3=1;//TZ3 will be one shot signal for EPWM1
EPwm2Regs.TZSEL.bit.OSHT3=1;//TZ3 will be one shot signal for EPWM2
EPwm1Regs.TZCTL.bit.TZA=2;//TZ will Force EPWM1A to a low state
EPwm1Regs.TZCTL.bit.TZB=2;//TZ will Force EPWM1B to a low state
EPwm2Regs.TZCTL.bit.TZA=2;//TZ will Force EPWM2A to a low state
EPwm2Regs.TZCTL.bit.TZB=2;//TZ will Force EPWM2B to a low state
// EPWM Module 2 config
EPwm2Regs.TBPRD = 600; // Period = 600 TBCLK counts
EPwm2Regs.TBPHS.half.TBPHS = 150; // Phase = 150/600 * 360 = 90 deg
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=90 deg)
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.CLKDIV=TB_DIV1;
EPwm2Regs.TBCTL.bit.HSPCLKDIV=TB_DIV1;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM2A
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complementary
EPwm2Regs.DBFED = 270; // FED = 20 TBCLKs
EPwm2Regs.DBRED = 270; // RED = 20 TBCLKs
EDIS;
}
void EPWM3_Init(void)
{
//
// Assumes ePWM3 clock is already enabled in InitSysCtrl();
//
EALLOW;
EPwm3Regs.TBPHS.half.TBPHS = 0; // Phase = 150/600 * 360 = 90 deg
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Symmetrical mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count DOWN on sync (=90 deg)
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm3Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // Select SOC from from zero on upcount
EPwm3Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on 1st event
EPwm3Regs.CMPA.half.CMPA = 150; // Set compare A value
EPwm3Regs.TBPRD = 600; // Set period for ePWM3
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // count up and start
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EDIS;
}
void EPWM4_Init(void)
{
//
// Assumes ePWM4 clock is already enabled in InitSysCtrl();
//
EALLOW;
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm4Regs.TBPRD = 1500; // Set period for ePWM3 60M/40k=1500
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // count up and start
EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1th event
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EDIS;
}
//use as DA output
void EPWM5_Init(void)
{
EALLOW;
EPwm5Regs.TBPRD = 1024; // Period = 1024 TBCLK counts
EPwm5Regs.CMPA.half.CMPA = 0; // Compare A = 350 TBCLK counts
EPwm5Regs.CMPB = 0; // Compare B = 200 TBCLK counts
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm5Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EDIS;
}
void ADC_Init(void)
{
EALLOW;
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP=1;//AD no overlap ADCNONOVERLAP
AdcRegs.ADCCTL2.bit.CLKDIV2EN=0; //CLKDIV2EN
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN0=1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN2=1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN4=1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN6=1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN8=1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN10=1;
AdcRegs.ADCSAMPLEMODE.bit.SIMULEN12=1;
AdcRegs.ADCSOC0CTL.bit.CHSEL = 3; //set SOC0 channel select to ADCINA0 ADCINB0
AdcRegs.ADCSOC2CTL.bit.CHSEL = 0; //set SOC2 channel select to ADCINA0 ADCINB0
AdcRegs.ADCSOC4CTL.bit.CHSEL = 1; //set SOC4 channel select to ADCINA1 ADCINB1
AdcRegs.ADCSOC6CTL.bit.CHSEL = 3; //set SOC6 channel select to ADCINA3 ADCINB3
AdcRegs.ADCSOC8CTL.bit.CHSEL = 5; //set SOC8 channel select to ADCINA5 ADCINB5
AdcRegs.ADCSOC10CTL.bit.CHSEL = 7; //set SOC10 channel select to ADCINA7 ADCINB7
AdcRegs.ADCSOC12CTL.bit.CHSEL = 7; //set SOC12 channel select to ADCINA7 ADCINB7
//
// set SOC0 start trigger on EPWM3A,
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0x0A;
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 0x0A;
AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 0x0A;
AdcRegs.ADCSOC6CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC7CTL.bit.TRIGSEL = 0x0A;
AdcRegs.ADCSOC8CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC9CTL.bit.TRIGSEL = 0x0A;
AdcRegs.ADCSOC10CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC11CTL.bit.TRIGSEL = 0x0A;
AdcRegs.ADCSOC12CTL.bit.TRIGSEL = 0x09;
// AdcRegs.ADCSOC13CTL.bit.TRIGSEL = 0x0A;
// set SOC0 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC0CTL.bit.ACQPS = 8;
// set SOC1 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 8;
// set SOC2 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC2CTL.bit.ACQPS = 8;
// set SOC3 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC3CTL.bit.ACQPS = 8;
// set SOC4 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC4CTL.bit.ACQPS = 8;
// set SOC5 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC5CTL.bit.ACQPS = 8;
// set SOC6 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC6CTL.bit.ACQPS = 8;
// set SOC7 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC7CTL.bit.ACQPS = 8;
// set SOC8 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC8CTL.bit.ACQPS = 8;
// set SOC9 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC9CTL.bit.ACQPS = 8;
// set SOC10 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC10CTL.bit.ACQPS = 8;
// set SOC11 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC11CTL.bit.ACQPS = 8;
// set SOC10 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC12CTL.bit.ACQPS = 8;
// set SOC11 S/H Window to 9 ADC Clock Cycles, (8 ACQPS plus 1)
AdcRegs.ADCSOC13CTL.bit.ACQPS = 8;
EDIS;
}
void GPIO_Init(void)
{
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0=0; //PWM1A->GPIO0
GpioCtrlRegs.GPAMUX1.bit.GPIO1=0; //PWM1B GPIO1
GpioCtrlRegs.GPAMUX1.bit.GPIO2=0; //PWM2A GPIO2
GpioCtrlRegs.GPAMUX1.bit.GPIO3=0; //PWM2B->GPIO3
GpioCtrlRegs.GPADIR.bit.GPIO0=1;//GPIO0->output
GpioCtrlRegs.GPADIR.bit.GPIO1=1;//GPIO1->output
GpioCtrlRegs.GPADIR.bit.GPIO2=1;//GPIO2->output
GpioCtrlRegs.GPADIR.bit.GPIO3=1;//GPIO3->output
GpioDataRegs.GPACLEAR.bit.GPIO0=1;
GpioDataRegs.GPACLEAR.bit.GPIO1=1;
GpioDataRegs.GPACLEAR.bit.GPIO2=1;
GpioDataRegs.GPACLEAR.bit.GPIO3=1;
//Set LED_Green Yellow RED
GpioCtrlRegs.GPAMUX2.bit.GPIO22=0; //GPIO22->LED_RED output
GpioCtrlRegs.GPADIR.bit.GPIO22=1;//GPIO22->LED_RED output
GpioCtrlRegs.GPBMUX1.bit.GPIO32=0; //GPIO32->LED_Green output
GpioCtrlRegs.GPBDIR.bit.GPIO32=1;//GPIO32->LED_Green output
GpioCtrlRegs.GPBMUX1.bit.GPIO33=0; //GPIO33->LED_Yellow output
GpioCtrlRegs.GPBDIR.bit.GPIO33=1;//GPIO33->LED_Yellow output
//Set AIO2/4/6/10/12/14 need to be configured chenmi 0908
GpioCtrlRegs.AIOMUX1.bit.AIO2 = 2; // AIO2 for CMP1A operation (AIO2=2 or 3 both used as ANA2 or COMP1A)
GpioCtrlRegs.GPBMUX1.bit.GPIO42=3; //GPIO42->COMP1_out
Comp1Regs.COMPCTL.bit.SYNCSEL = 1;
Comp1Regs.COMPCTL.bit.QUALSEL = 0x0001;
Comp1Regs.COMPCTL.bit.COMPSOURCE=0;//Inverting input of comparator connected to internal DAC
Comp1Regs.COMPCTL.bit.COMPDACEN=1;
Comp1Regs.COMPCTL.bit.CMPINV=1;//Inverted output of comparator is passed
Comp1Regs.DACCTL.bit.DACSOURCE=0;//DAC controlled by DACVAL
Comp1Regs.DACVAL.bit.DACVAL=620;//40A/66*1024=620 HW_OCP recoverable
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3;//set GPIO17 AS TZ3
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1;//set GPIO13 AS TZ2
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1;//set GPIO15 AS TZ1
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2)
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ1)
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ3)
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ1)
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2)
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ3)
EDIS;
}
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