FPGA采集模拟信号数据波形,51单片机显示波形 -

/*==============================================
* 描述:频率计控制模块计数测试程序
//==============================================*/
module frqent_count(clk_b,clk_d,vavle,rst,cnt_h_out,cnt_b_out,cnt_d_out);
input rst;
input clk_b;
input clk_d;
input vavle;
output reg[31:0] cnt_h_out; //用于测量高脉宽
output reg[31:0] cnt_b_out; //标准频率计数
output reg[31:0] cnt_d_out; //待测频率计数
reg [31:0] cnt_h; //用于测量高脉宽
reg [31:0] cnt_b; //标准频率计数
reg [31:0] cnt_d; //待测频率计数
reg start_reg; //开始信号缓存
reg clk_d_reg; //待测时钟缓存
wire start;
/*------------------------------------------------
* 模块说明:计数允许模块
* 备注:Start_l对于频率没有作用,只对于低电平
脉宽计数有作用,频率主要作用在Start
*-------------------------------------------------*/
assign start = vavle;
//开始信号缓存
always@(posedge clk_b,negedge rst)
begin
if(!rst)
begin
start_reg <= 1'b0;
end
else
begin
start_reg <= start;
end
end
//待测信号缓存
always@(posedge clk_b, negedge rst)
begin
if(!rst)
begin
clk_d_reg <= 1'b0;
end
else
begin
clk_d_reg <= clk_d;
end
end
//待测时钟进行计数
always@(posedge clk_d,negedge rst)
begin
if(!rst)
begin
cnt_d <= 32'b0;
end
else
begin
if(start == 0)
begin
cnt_d <= 0;
end
// 高电平触发
else
begin
cnt_d <= cnt_d + 1'b1;
end
end
end
//标准时钟进行计数
always@(posedge clk_b,negedge rst)
begin
if(!rst)
begin
cnt_b <= 0;
end
else
begin
if(start == 0)
begin
cnt_b <= 0;
end
else
begin
cnt_b <= cnt_b + 1'b1;
end
end
end
//高电平计数
always@(posedge clk_b, negedge rst)
begin
if(!rst)
begin
cnt_h <= 0;
end
else
begin
if(clk_d == 0)
begin
cnt_h <= 0;
end
else
begin
cnt_h <= cnt_h + 1'b1;
end
end
end
//标准计数和待测计数输出
always@(posedge clk_b, negedge rst)
begin
if(!rst)
begin
cnt_b_out <= 0;
cnt_b_out <= 0;
end
else
begin
if(start_reg && !start)
begin
cnt_b_out <= cnt_b;
cnt_d_out <= cnt_d;
end
else
begin
cnt_b_out <= cnt_b_out;
cnt_d_out <= cnt_d_out;
end
end
end
//高电平计数输出
always@(posedge clk_b,negedge rst)
begin
if(!rst)
begin
cnt_h_out<=0;
end
else
begin
if(clk_d_reg&&!clk_d)
begin
cnt_h_out<=cnt_h;
end
else
begin
cnt_h_out<=cnt_h_out;
end
end
end
endmodule

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