定时计数器的Verilog代码 -

标题: 定时计数器的Verilog代码 [打印本页]

作者: zfyzfyzfy 时间: 2018-11-4 20:12
标题: 定时计数器的Verilog代码
`timescale 1ns / 1ps
`define  ENABLE          1'b1
`define  DISABLE          1'b0
`define  HIGH             1'b1
`define  LOW             1'b0
`define  DATA_W    8
`define  EA    7
`define  TF    6
`define  ET0    0
`define  ET1    1
`define  OV    2
module timer_counter(
input wire       clk,
input wire       reset,
input wire       count,
input wire  [`DATA_W-1:0]    th,
input wire  [`DATA_W-1:0]    tl,
input wire  [`DATA_W-1:0]    tmod,
input wire  [`DATA_W-1:0]    ie,
output  wire                   mul,
output reg          irq_timer0,
output reg          irq_timer1

);
reg [`DATA_W-1:0] th0;
reg [`DATA_W-1:0] tl0;
wire    flag;
reg    a,b;
always @(posedge clk)
begin
if(!reset)
begin
th0<=8'h0;
tl0<=8'h0;
irq_timer1<=`DISABLE;
end
else if(ie [`EA])
if(ie [`TF])
begin
if(tmod[1]==`LOW)
begin
  if((tmod [0]==`LOW)&&(ie [`ET0]==`ENABLE))
  begin
if((16'hFFFF-{th,tl})=={th0,tl0})
begin
tl0<=8'h0;
th0<=8'h0;
irq_timer0<=`ENABLE;
// ov    <=`ENABLE;
end
else  {th0,tl0}<={th0,tl0}+1;

  end
  else if((tmod [0]==`HIGH)&&(ie [`ET1]==`HIGH))
  begin
if(tl0==8'hFF)
begin
tl0  <=8'h0;
irq_timer1<=`ENABLE;
  //  ov       <=`ENABLE;
end
else  tl0<=tl0+1;
  end
end
else if(tmod [1]==`HIGH)
begin
if((tmod [0]==`LOW)&&(ie [`ET0]==`ENABLE)&&flag)
  begin
if((16'hFFFF-{th,tl})=={th0,tl0})
begin
tl0<=8'h0;
th0<=8'h0;
irq_timer0<=`ENABLE;
// ov    <=`ENABLE;
end
else  {th0,tl0}<={th0,tl0}+1;

  end
  else if((tmod [0]==`HIGH)&&(ie [`ET1]==`HIGH))
  begin
if({tl0}==8'hFF)
begin
irq_timer1  <=`ENABLE;
tl0<=8'h0;
  //  ov       <=`ENABLE;
end
else  tl0<=tl0+1;
  end
end
end
else begin
irq_timer0<=`DISABLE;
irq_timer1<=`DISABLE;
tl0<=8'h0;
         th0<=8'h0;
end
end
always @(*)
begin
a<=count;
b<=a;
end
//assign irq_timer0=c&&!d;
assign flag=a&&!b;
assign mul=tmod [0]&&ie [`ET1]&&ie [`EA]&&ie [`TF];
endmodule

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