我的颜色空间变换YCBCR to RGB 设计Verilog代码 -

`timescale 1ps/1ps
module YCbCr2RGB (
//iRESET,
iCLK,
iY,
iCb,
iCr,
Red,
Green,
Blue
);
//csc1
//scale up to 10bit = 1024
parameter R_Y_CST = 18'h004A8,
R_CB_CST = 18'h00000,
R_CR_CST = 18'h00662;
parameter G_Y_CST = 18'h004A8,
G_CB_CST = 18'h3FE70,
G_CR_CST = 18'h3FCBF;
parameter B_Y_CST = 18'h004A8,
B_CB_CST = 18'h00812,
B_CR_CST = 18'h00000;
parameter R_CST = 228262; //183763; // 183251;//227750 228352 228262
parameter G_CST = 138740; //138710;//139222;//139252 139264 138740
parameter B_CST = 283574; //232260;//231748; //283062 283648 283574
////csc2
//parameter R_Y_CST = 18'h00400,
// R_CB_CST = 18'h00000,
// R_CR_CST = 18'H0059C;
//
//parameter G_Y_CST = 18'h00400,
// G_CB_CST = 18'H3FEA0,
// G_CR_CST = 18'H3FD25;
//
//parameter B_Y_CST = 18'h00400,
// B_CB_CST = 18'H00717,
// B_CR_CST = 18'h00000;
//
//parameter R_CST = 183763; // 183251;//227750 228352 228262
//parameter G_CST = 138710;//139222;//139252 139264 138740
//parameter B_CST = 232260;//231748; //283062 283648 283574
parameter CST_YUV_Prec = 10;
//// scale up to 12bit = 4096
//parameter R_Y_CST = 20'h012A0,
// R_CB_CST = 20'h00000,
// R_CR_CST = 20'h01989;
//
//parameter G_Y_CST = 20'h012A0,
// G_CB_CST = 20'hFF9BE,
// G_CR_CST = 20'hFF2FE;
//
//parameter B_Y_CST = 20'h012A0,
// B_CB_CST = 20'h0204A,
// B_CR_CST = 20'h00000;
//
//parameter R_CST = 911000,
// G_CST = 557007,
// B_CST = 1132249;
//
//parameter CST_YUV_Prec = 12;
//csc1
//R = 1.164*Y + 1.596*CR - 222.912
//G = 1.164*Y - 0.391*CB - 0.813*CR + 135.488
//B = 1.164*Y + 2.018*CB - 276.928
//csc2
//R = Y + 1.402*V - 179.456
//G = Y - 0.34413*U - 0.71414*V + 135.45856
//B = Y + 1.772*U - 226.816
// Input
input [7:0] iY,iCb,iCr;
input iCLK; //iRESET,
// Output
output [7:0] Red,Green,Blue;
// Internal Registers/Wires
reg [7:0] oRed,oGreen,oBlue;
reg [17:0] X_OUT,Y_OUT,Z_OUT;
wire [27:0] X,Y,Z;
assign Red = oRed;//[9:2];
assign Green= oGreen;//[9:2];
assign Blue = oBlue;//[9:2];
wire [7:0] Y1,Cb1,Cr1;
assign Y1 = iY ; //huang210;//LAN41;//LV145;//QING170;//iY; //iY;
assign Cb1 = iCb;// 16; //240;//54; //166; //iCb;//iCb; //(R) (82 , 90 240)
assign Cr1 = iCr;// 146;//110;//34; //16; //iCr;//iCr; //(R+G)(210 16 146 ) //(GLUE 41 240 110) //{GREEN 145 54 34}
always@(posedge iCLK )//,posedge iRESET)
begin
// if(iRESET)
// begin
// oRed<=0;
// oGreen<=0;
// oBlue<=0;
// end
// else
// begin
// Red
if(X_OUT[17])
oRed<=0;
else if(X_OUT[16:0]>255)
oRed<=255;
else
oRed<=X_OUT[7:0];
// Green
if(Y_OUT[17])
oGreen<=0;
else if(Y_OUT[16:0]>255)
oGreen<=255;
else
oGreen<=Y_OUT[7:0];
// Blue
if(Z_OUT[17])
oBlue<=0;
else if(Z_OUT[16:0]>255)
oBlue<=255;
else
oBlue<=Z_OUT[7:0];
// end
end
always@(posedge iCLK )//,posedge iRESET)
begin
// if(iRESET)
// begin
// X_OUT<=0;
// Y_OUT<=0;
// Z_OUT<=0;
// end
// else
begin
X_OUT <= ((X - R_CST) >> (CST_YUV_Prec)); // ((( X - R_CST ) % 1024) >= 512) ? (((X - R_CST + 512) >> (CST_YUV_Prec)) ) :
Y_OUT <= ((Y + G_CST) >> (CST_YUV_Prec)); // ((( Y + G_CST ) % 1024) >= 512) ? (((Y + G_CST + 512) >> (CST_YUV_Prec)) ) :
Z_OUT <= ((Z - B_CST) >> (CST_YUV_Prec)); // ((( Z - B_CST ) % 1024) >= 512) ? (((Z - B_CST + 512) >> (CST_YUV_Prec)) ) :
end
end
//wire mac_reset ;
//assign mac_reset = (iRESET) ;
MAC_10 MAC_3_X (
//.aclr0(mac_reset),
.clock0(iCLK),
.dataa_0(Y1),
.dataa_1(Cb1),
.dataa_2(Cr1),
.datab_0(R_Y_CST),
.datab_1(R_CB_CST),
.datab_2(R_CR_CST),
.result(X)
);
MAC_10 MAC_3_Y (
/// .aclr0(mac_reset),
.clock0(iCLK),
.dataa_0(Y1),
.dataa_1(Cb1),
.dataa_2(Cr1),
.datab_0(G_Y_CST),
.datab_1(G_CB_CST),
.datab_2(G_CR_CST),
.result(Y)
);
MAC_10 MAC_3_Z (
// .aclr0(mac_reset),
.clock0(iCLK),
.dataa_0(Y1),
.dataa_1(Cb1),
.dataa_2(Cr1),
.datab_0(B_Y_CST),
.datab_1(B_CB_CST),
.datab_2(B_CR_CST),
.result(Z)
);
endmodule

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