我的数字电位器FPGA verilog i2c控制设计含源码文档原理图 -

`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:59:53 02/12/2019
// Design Name:
// Module Name: IIC
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IIC(
clk_sys,
rst_n,
//key_wr,
//key_rd,
eeprom_scl,
//led,
eeprom_sda
);
input clk_sys;
input rst_n;
//input key_rd;
//input key_wr;
output reg eeprom_scl;
//output [3:0] led;
//output reg [7:0] result; //256
//output reg led;
inout eeprom_sda;
//reg [3:0] led;
reg clk;
reg [7:0] cnt;//256
reg [7:0] state;//256
reg [3:0] counter;//16
reg link_sda;
reg wr;
//reg rd;
reg sda_buf;
reg [7:0] data;
//reg [24:0] Cl; // C1 延时计数器
//wire C1_Clk; // 产生一个脉动时钟
//assign Cl_Clk = (Cl == 25'd24999999 ) ? 1 : 0;
assign eeprom_sda = (link_sda)?sda_buf:1'hz;
always @ ( negedge clk_sys or negedge rst_n)
begin
if(!rst_n)
begin
clk <= 0;
cnt <= 0;
//Cl <= 0;
end
else
begin
if(cnt<249)
cnt <= cnt + 1'b1;
else
begin
clk <= ~clk;
cnt <= 0;
end
//if(Cl<25'd24999999)Cl <= Cl + 1'b1;
//else Cl <= 25'd0;
end
end//250*20ns=5000ns=5us=200KHZ;5us*2=10Us=100KHZ;
always @(negedge clk or negedge rst_n)
begin
if(!rst_n)
begin
eeprom_scl <= 0;
end
else
eeprom_scl <= ~eeprom_scl;
end//50KHz=20us=20000ns
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state <= 0;
link_sda <= 0;
sda_buf <= 0;
counter <= 0;
wr <= 1;
//led = 1;
//rd <= 0;
//result <= 0;
data <= 0;
//led <= 4'b0001;
end
else
begin
case(state)
0:begin
wr <= 1;
if(!eeprom_scl)
begin
link_sda <= 1;
sda_buf <= 1;
state <= 1;
end
end
1:begin
if(eeprom_scl)
begin
sda_buf <= 0;
state <= 2;
data <= 8'b10100000;
end
end
2:begin
if((counter<8)&&(!eeprom_scl))
begin
counter <= counter + 1'b1;
data <= {data[6:0],data[7]};
sda_buf <= data[7];
end
else if((counter == 8)&&(!eeprom_scl))
begin
counter <= 0;
state <= 3;
link_sda <= 0;
end
end
3:begin
if(eeprom_scl)
begin
if(!eeprom_sda)
begin
state <= 4;
data <= 8'h00;//μ??·
end
end
end
4:begin
link_sda <= 1;
if((counter < 8)&&(!eeprom_scl))
begin
counter <= counter + 1'b1;
data <= {data[6:0],data[7]};
sda_buf <= data[7];
end
else if ((counter == 8)&&(!eeprom_scl))
begin
counter <= 0;
state <= 5;
link_sda <= 0;
sda_buf <= 1;
end
end//
5:begin
if(eeprom_scl)
begin
if(!eeprom_sda)
begin
if(wr == 1)
begin
state <= 6;
end
data <= 8'b00000101;//
end
end
end
6:begin
link_sda <= 1;
if((counter < 8)&&(!eeprom_scl))
begin
counter <= counter + 1'b1;
data <= {data[6:0], data[7]};
sda_buf <= data[7];
end
else if((counter == 8)&&(!eeprom_scl))
begin
counter <= 0;
state <= 7;
link_sda <= 0;
end
end
7:begin
if(eeprom_scl)
begin
if(!eeprom_sda)
state <= 8;
end
end
8:begin
link_sda <= 1;
sda_buf <= 0;//先拉低，再拉高；
if(eeprom_scl)
begin
//led <= 0;
sda_buf <= 1;
state <= 0;
//wr <= 0;
//led <= 4'b0100;
//led[0] <= 1;
//led[1] <= 0;
end
//if(Cl_Clk)led[3] <= ~led[3];
end
default : state <= 0;
endcase
end
end
endmodule

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