Verilog新手，遇到了error解决不了 -

标题: Verilog新手，遇到了error解决不了 [打印本页]

作者: 123gkhkhkhkhgg 时间: 2019-5-26 22:26
标题: Verilog新手，遇到了error解决不了
'include "file.v"
'timescale 10ns/100ps
module cnt_test();
  reg [4:0] data;
  reg rst,load,clk;
  wire [4:0] dout;
  'define period 10
  cnt c1(.dout(dout),.clk(clk),.rst(rst),.load(load));
  initial
  clk=0;
  always
  begin
#5 clk=1'b1;
#5 clk=1'b0;
  end
  initial
  begin
data=5'h15;
load=0;
rst=1;
#'period rst=0;
#('period*5) data=5'h1d;
load-1;
#'period load=0;
#('period*50)
$finish;
  end
endmodule

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