标题: fpga优先级编码器 [打印本页]
作者: 柠檬兔 时间: 2020-5-29 00:09
标题: fpga优先级编码器
module clock(ctr,yout,clk,clr);
input clk,clr;
output[6:0] yout;
output[1:0] ctr;
reg[6:0] yout;
reg[4:1] temp;
reg[4:1] temp_a,temp_b;
reg[1:0] ctr;
reg state;
reg c;
reg[10:0] cp;
parameter s0=2'h0,s1=2'h1;
always @ (posedge clk or negedge clr)
begin
if(!clr)
begin
state=s0 ;
ctr=0 ;
end
else
begin
case (state)
s0:begin ctr=2'b10; temp=temp_a; state=s1; end
s1:begin ctr=2'b01; temp=temp_b; state=s0; end
endcase
if(cp==2)
begin
c=1;
cp=0;
end
else
begin
cp=cp+1;
c=0;
end
end
end
always @(posedge clk )
begin
if(!clr){temp_a,temp_b}=0;
else
begin
if(c==1)
begin
if({temp_a,temp_b}==8'h59) {temp_a,temp_b}=0;
else if(temp_b==9)
begin
temp_b=0;temp_a=temp_a+1;
end
else temp_b=temp_b+1;
end
end
end
always @ (temp)
begin
case(temp)
4'd0:yout=7'b1111110;
4'd1:yout=7'b0110000;
4'd2:yout=7'b1101101;
4'd3:yout=7'b1111001;
4'd4:yout=7'b0110011;
4'd5:yout=7'b1011011;
4'd6:yout=7'b1011111;
4'd7:yout=7'b1110000;
4'd8:yout=7'b1111111;
4'd9:yout=7'b1111011;
default:yout=7'b0000000;
endcase
end
endmodule
其余部分程序：
1.10进制计数器文本输入
module CNT10(clk,clr,en,cout,q);
input clk,en,clr;
output[3:0] q;
output cout;
reg [3:0] q1;
reg cout;
assign q= q1;
always @(posedge clk or negedge clr)
begin
if (!clr) q1<=0;
else if(en)
begin
if(q1<9) q1<=q1+1;
else q1<=4'b0000;
end
end
always @(q1)
if (q1==4'h9)
cout= 1'b1;
else
cout= 1'b0;
endmodule
2.8-3优先级编码器
Case语句实现
module bm8_3 ( din ,yout);
input [7:0] din ;
wire [7:0] din ;
output [2:0] yout ;
reg [2:0] yout;
always @ ( din )
begin
case ( din )
8'b0000_0001 : b<=3'b000;
8'b0000_0010 : b<=3'b001;
8'b0000_0100 : b<=3'b010;
8'b0000_1000 : b<=3'b011;
8'b0001_0000 : b<=3'b100;
8'b0010_0000 : b<=3'b101;
8'b0100_0000 : b<=3'b110;
8'b1000_0000 : b<= 3'b111;
default : b<= 3'b000;
endcase
end
endmodule
if语句实现
module yxbm8_3 ( A ,I ,GS ,EO ,EI );
input [7:0] I ;
wire [7:0] I ;
output [2:0] A ;
reg [2:0] A ;
always @ ( I )
if ( I[0] == 0 )
A <= 3'b000;
else if ( I[1] == 0 )
A <= 3'b001;
else if ( I[2] == 0 )
A <= 3'b010;
else if ( I[3] == 0 )
A <= 3'b011;
else if ( I[4] == 0 )
A <= 3'b100;
else if ( I[5] == 0 )
A <= 3'b101;
else if ( I[6] == 0 )
A <= 3'b110;
else if ( I[7] == 0 )
A <= 3'b111;
else if ( I == 8'b11111111)
A <= 3'b111;
end
endmodule
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