标题: FFT变换的IP核的vhdl源代码 [打印本页]
作者: zxopenljx    时间: 2021-1-15 14:01
标题: FFT变换的IP核的vhdl源代码
  1. library ieee ;
  2. use ieee.std_logic_1164.all ;
  3. use ieee.std_logic_arith.all ;
  4. use work.butter_lib.all ;

  6. entity control_main is
  7. port (
  8.        a_small , sign_a , sign_b : in std_logic ;
  9.        sign_out , add_sub , reset_all : out std_logic ;
  10.        en_sub , en_swap , en_shift , addpulse , normalise : out std_logic ;
  11.        fin_sub , fin_swap , finish_shift , add_finish , end_all : in std_logic ;
  12.        clock_main , clock , reset , enbl , zero_num , change: in std_logic ) ;
  13. end control_main ;

  15. architecture rtl of control_main is
  16. signal current_state , next_state : state ;
  17. begin
  18. process (current_state , add_finish , finish_shift , end_all , enbl , clock_main , fin_sub , fin_swap , zero_num , change)
  19. begin

  21. case current_state is
  22. when reset1 =>
  23.   if( enbl = '1' and clock_main = '1') then
  24.   normalise <= '0' ;
  25.   addpulse <= '0' ;
  26.   reset_all <= '1' ;
  27.   next_state <= reset2 ;
  28.   elsif ( enbl = '0') then
  29.   next_state <= reset7 ;-- last state to exit
  30.   else
  31.   next_state <= reset1 ;
  32.   end if ;

  34. when reset2 =>
  35.   reset_all <= '0' ; -- else values willnot cchange
  36.   en_sub <= '1' ;
  37.   en_swap <= '1' ;
  38.   next_state <= reset3 ;

  40. when reset3 =>
  41.   if (zero_num = '1') then
  42.   next_state <= reset5 ;
  43.   en_sub <= '0' ;
  44.   en_swap <= '0' ;
  45.   elsif(fin_sub= '1') then
  46.   if(fin_swap = '1') then
  47.   en_shift <= '1' ;
  48.   en_sub <= '0' ;
  49.   en_swap <= '0' ;
  50.   next_state <= reset4 ;
  51.   end if ;
  52.   else
  53.   next_state <= reset3 ;
  54.   end if ;
  55.   
  56. when reset4 =>
  57. if (finish_shift = '1') then
  58. en_shift <= '0' ;
  59. addpulse <= '1' ;
  60. next_state <= reset5 ;
  61. else
  62. next_state <= reset4 ;
  63. end if ;

  65. when reset5 =>
  66. if (zero_num = '1') then
  67. normalise <= '1' ;
  68. next_state <= reset6 ;
  69. elsif (add_finish = '1') then
  70. normalise <= '1' ;
  71. addpulse <= '0' ;
  72. next_state <= reset6 ;
  73. else
  74. next_state <= reset5 ;
  75. end if ;

  77. when reset6 =>
  78. if (end_all = '1' and clock_main = '1') then
  79. normalise <= '0' ;
  80. next_state <= reset6 ;
  81. elsif (end_all = '1' and clock_main = '0') then
  82. next_state <= reset1 ;
  83. else
  84. next_state <= reset6 ;
  85. end if ;

  87. when reset7 =>
  88. next_state <= reset7 ;

  90. when others =>
  91. next_state <= reset1 ;

  93. end case ;
  94. end process ;

  96. process(clock , reset , change)
  97. begin
  98. if(change = '1') then
  99. current_state <= reset1 ;
  100. elsif (reset = '1') then
  101. current_state <= reset1 ;
  102. elsif (clock= '1' and clock'event) then
  103. current_state <= next_state ;
  104. end if ;
  105. end process ;

  107. process (a_small , sign_a , sign_b)
  108. begin
  109. if (sign_a = '0' and sign_b = '0') then
  110. sign_out <= '0' ;
  111. add_sub <= '1' ;

  113. elsif (sign_a = '1' and sign_b = '1') then
  114. sign_out <= '1' ;
  115. add_sub <= '1' ;

  117. elsif (a_small = '1' and sign_a = '0') then
  118. sign_out <= '1' ;
  119. add_sub <= '0' ;

  121. elsif (a_small = '0' and sign_a = '1') then
  122. sign_out <= '1' ;
  123. add_sub <= '0' ;

  125. else
  126. sign_out <= '0' ;
  127. add_sub <= '0' ;
  128. end if ;

  130. end process ;

  132. end rtl ;
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FFT变换的IP核的源代码.zip

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FFT变换的IP核的源代码.zip



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