VHDL除法器宏模块及编程调用 -

标题: VHDL除法器宏模块及编程调用 [打印本页]

作者: heicad 时间: 2014-10-17 18:51
标题: VHDL除法器宏模块及编程调用
1.在要调用项目的文件夹创建除法器宏模块
按下图设置和添加宏模块

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity dddd is
Port(a:in std_logic_vector(6 downto 0);
   b:in std_logic_vector(3 downto 0);
x:out std_logic_vector(6 downto 0);
y:out std_logic_vector(3 downto 0));
end ;
architecture dd of dddd is
--------定义调用宏模块
component chufa is
port(numer:in std_logic_vector(6 downto 0);
   denom:in std_logic_vector(3 downto 0);
quotient:out std_logic_vector(6 downto 0);
   remain:out std_logic_vector(3 downto 0) );
end component;
-----------------结束定义
begin
U:chufa port map(a,b,x,y);  -----调用
end;

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