标题: LPC11xx单片机系统配置_system_LPC11xx.c [打印本页] 作者: huge 时间: 2015-2-18 23:07 标题: LPC11xx单片机系统配置_system_LPC11xx.c /******************************************************************************
* @file: system_LPC11xx.c
* @purpose: CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the NXP LPC11xx Device Series
* @version: V1.0
* @date: 26. Nov. 2008
*----------------------------------------------------------------------------
*
* Copyright (C) 2008 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC11xx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Controls and Status Register (SCS)
// <o1.4> OSCRANGE: Main Oscillator Range Select
// <0=> 1 MHz to 20 MHz
// <1=> 15 MHz to 24 MHz
// <e1.5> OSCEN: Main Oscillator Enable
// </e>
// </h>
//
// <h> Clock Source Select Register (CLKSRCSEL)
// <o2.0..1> CLKSRC: PLL Clock Source Selection
// <0=> Internal RC oscillator
// <1=> Main oscillator
// <2=> RTC oscillator
// </h>
//
// <e3> PLL0 Configuration (Main PLL)
// <h> PLL0 Configuration Register (PLL0CFG)
// <i> F_cco0 = (2 * M * F_in) / N
// <i> F_in must be in the range of 32 kHz to 50 MHz
// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
// <o4.0..14> MSEL: PLL Multiplier Selection
// <6-32768><#-1>
// <i> M Value
// <o4.16..23> NSEL: PLL Divider Selection
// <1-256><#-1>
// <i> N Value
// </h>
// </e>
//
//
// <h> CPU Clock Configuration Register (CCLKCFG)
// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
// <0-255>
// <i> Divide is CCLKSEL + 1. Only 0 and odd values are valid.
// </h>
//
//
// </e>
*/
#define CLOCK_SETUP 0
#define MAIN_PLL_SETUP 0
#define MAIN_CLKSRCSEL_Val 0x00000001
#define MAIN_PLL_M_Val 0x00000003
#define MAIN_PLL_P_Val 0x00000001
#define SYS_AHB_DIV_Val 1 /* 1 through 255, typical is 1 or 2 or 4 */
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/* Enable main system PLL, main system PLL bit 7 in PDRUNCFG. */
LPC_SYSCON->PDRUNCFG &= ~(0x1<<7); /* PDRUNCFG第七位写0,即系统PLL上电 */
while ( !(LPC_SYSCON->SYSPLLSTAT & 0x01) ); /* Wait until it's locked */
/* main system OSC run is cleared, bit 5 in PDRUNCFG register */
LPC_SYSCON->PDRUNCFG &= ~(0x1<<5); /* PDRUNCFG的第五位写0,即系统振荡器上电 */
/* Wait 200us for OSC to be stablized, no status indication, dummy wait. */
for ( i = 0; i < 0x100; i++ );
#if (MAIN_PLL_SETUP)
Main_PLL_Setup();
#endif
#endif /* endif CLOCK_SETUP */
/* System clock to the IOCON needs to be enabled or most of the I/O related peripherals won't work. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); //使能IO配置模块的时钟
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8); //开启定时器Timer16_1时钟
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5); //开启I2C模块时钟