stm32f10x.h文件代码分析 - - Powered by Discuz!

* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
外设分为内核外设和芯片级外设。这个头文件是芯片级外设方位层的头文件
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F10x Connectivity line,
* High density, High density value line, Medium density,
* Medium density Value line, Low density, Low density Value line
* and XL-density devices.
这个文件为STM32F10x所有系列的芯片级外设寄存器做定义、寄存器位做定义。
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
应用编程者在使用c语言编写代码的时候，这个文件是唯一需要包含的文件，它包括：
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral抯 drivers in application code(i.e.
* code will be based on direct access to peripheral抯 registers
* rather than drivers API), this option is controlled by
* "#define USE_STDPERIPH_DRIVER"
* - To change few application-specific parameters such as the HSE
* crystal frequency
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral抯 registers hardware
* 一些配置段，这些配置段允许我们选择一下内容：
选择目标应用中使用的芯片
选择是使用库函数还是直接寄存器访问，这个是由"#define USE_STDPERIPH_DRIVER"控制的
外设寄存器的结构体数据类型的定义以及地址映射
外设寄存器的声明和位定义
访问外设寄存器的宏定义
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
*
© COPYRIGHT 2011 STMicroelectronics
******************************************************************************
*/
#ifndef __STM32F10x_H
#define __STM32F10x_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
#endif
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
#endif
#if !defined USE_STDPERIPH_DRIVER
#endif
#if !defined HSE_VALUE
#ifdef STM32F10X_CL
#define HSE_VALUE ((uint32_t)25000000)
#else
#define HSE_VALUE ((uint32_t)8000000)
#endif
#endif
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
#define HSI_VALUE ((uint32_t)8000000)
#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05)
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
#define __STM32F10X_STDPERIPH_VERSION_RC (0x00)
#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
|(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
|(__STM32F10X_STDPERIPH_VERSION_RC))
#ifdef STM32F10X_XL
#define __MPU_PRESENT 1
#else
#define __MPU_PRESENT 0
#endif
#define __NVIC_PRIO_BITS 4
#define __Vendor_SysTickConfig 0
typedef enum IRQn
{
NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WWDG_IRQn = 0,
PVD_IRQn = 1,
TAMPER_IRQn = 2,
RTC_IRQn = 3,
FLASH_IRQn = 4,
RCC_IRQn = 5,
EXTI0_IRQn = 6,
EXTI1_IRQn = 7,
EXTI2_IRQn = 8,
EXTI3_IRQn = 9,
EXTI4_IRQn = 10,
DMA1_Channel1_IRQn = 11,
DMA1_Channel2_IRQn = 12,
DMA1_Channel3_IRQn = 13,
DMA1_Channel4_IRQn = 14,
DMA1_Channel5_IRQn = 15,
DMA1_Channel6_IRQn = 16,
DMA1_Channel7_IRQn = 17,
#ifdef STM32F10X_LD
ADC1_2_IRQn = 18,
USB_HP_CAN1_TX_IRQn = 19,
USB_LP_CAN1_RX0_IRQn = 20,
CAN1_RX1_IRQn = 21,
CAN1_SCE_IRQn = 22,
EXTI9_5_IRQn = 23,
TIM1_BRK_IRQn = 24,
TIM1_UP_IRQn = 25,
TIM1_TRG_COM_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
SPI1_IRQn = 35,
USART1_IRQn = 37,
USART2_IRQn = 38,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
USBWakeUp_IRQn = 42
#endif
#ifdef STM32F10X_LD_VL
ADC1_IRQn = 18,
EXTI9_5_IRQn = 23,
TIM1_BRK_TIM15_IRQn = 24,
TIM1_UP_TIM16_IRQn = 25,
TIM1_TRG_COM_TIM17_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
SPI1_IRQn = 35,
USART1_IRQn = 37,
USART2_IRQn = 38,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
CEC_IRQn = 42,
TIM6_DAC_IRQn = 54,
TIM7_IRQn = 55
#endif
#ifdef STM32F10X_MD
ADC1_2_IRQn = 18,
USB_HP_CAN1_TX_IRQn = 19,
USB_LP_CAN1_RX0_IRQn = 20,
CAN1_RX1_IRQn = 21,
CAN1_SCE_IRQn = 22,
EXTI9_5_IRQn = 23,
TIM1_BRK_IRQn = 24,
TIM1_UP_IRQn = 25,
TIM1_TRG_COM_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
TIM4_IRQn = 30,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
I2C2_EV_IRQn = 33,
I2C2_ER_IRQn = 34,
SPI1_IRQn = 35,
SPI2_IRQn = 36,
USART1_IRQn = 37,
USART2_IRQn = 38,
USART3_IRQn = 39,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
USBWakeUp_IRQn = 42
#endif
#ifdef STM32F10X_MD_VL
ADC1_IRQn = 18,
EXTI9_5_IRQn = 23,
TIM1_BRK_TIM15_IRQn = 24,
TIM1_UP_TIM16_IRQn = 25,
TIM1_TRG_COM_TIM17_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
TIM4_IRQn = 30,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
I2C2_EV_IRQn = 33,
I2C2_ER_IRQn = 34,
SPI1_IRQn = 35,
SPI2_IRQn = 36,
USART1_IRQn = 37,
USART2_IRQn = 38,
USART3_IRQn = 39,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
CEC_IRQn = 42,
TIM6_DAC_IRQn = 54,
TIM7_IRQn = 55
#endif
#ifdef STM32F10X_HD
ADC1_2_IRQn = 18,
USB_HP_CAN1_TX_IRQn = 19,
USB_LP_CAN1_RX0_IRQn = 20,
CAN1_RX1_IRQn = 21,
CAN1_SCE_IRQn = 22,
EXTI9_5_IRQn = 23,
TIM1_BRK_IRQn = 24,
TIM1_UP_IRQn = 25,
TIM1_TRG_COM_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
TIM4_IRQn = 30,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
I2C2_EV_IRQn = 33,
I2C2_ER_IRQn = 34,
SPI1_IRQn = 35,
SPI2_IRQn = 36,
USART1_IRQn = 37,
USART2_IRQn = 38,
USART3_IRQn = 39,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
USBWakeUp_IRQn = 42,
TIM8_BRK_IRQn = 43,
TIM8_UP_IRQn = 44,
TIM8_TRG_COM_IRQn = 45,
TIM8_CC_IRQn = 46,
ADC3_IRQn = 47,
FSMC_IRQn = 48,
SDIO_IRQn = 49,
TIM5_IRQn = 50,
SPI3_IRQn = 51,
UART4_IRQn = 52,
UART5_IRQn = 53,
TIM6_IRQn = 54,
TIM7_IRQn = 55,
DMA2_Channel1_IRQn = 56,
DMA2_Channel2_IRQn = 57,
DMA2_Channel3_IRQn = 58,
DMA2_Channel4_5_IRQn = 59
#endif
#ifdef STM32F10X_HD_VL
ADC1_IRQn = 18,
EXTI9_5_IRQn = 23,
TIM1_BRK_TIM15_IRQn = 24,
TIM1_UP_TIM16_IRQn = 25,
TIM1_TRG_COM_TIM17_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
TIM4_IRQn = 30,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
I2C2_EV_IRQn = 33,
I2C2_ER_IRQn = 34,
SPI1_IRQn = 35,
SPI2_IRQn = 36,
USART1_IRQn = 37,
USART2_IRQn = 38,
USART3_IRQn = 39,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
CEC_IRQn = 42,
TIM12_IRQn = 43,
TIM13_IRQn = 44,
TIM14_IRQn = 45,
TIM5_IRQn = 50,
SPI3_IRQn = 51,
UART4_IRQn = 52,
UART5_IRQn = 53,
TIM6_DAC_IRQn = 54,
TIM7_IRQn = 55,
DMA2_Channel1_IRQn = 56,
DMA2_Channel2_IRQn = 57,
DMA2_Channel3_IRQn = 58,
DMA2_Channel4_5_IRQn = 59,
DMA2_Channel5_IRQn = 60
#endif
#ifdef STM32F10X_XL
ADC1_2_IRQn = 18,
USB_HP_CAN1_TX_IRQn = 19,
USB_LP_CAN1_RX0_IRQn = 20,
CAN1_RX1_IRQn = 21,
CAN1_SCE_IRQn = 22,
EXTI9_5_IRQn = 23,
TIM1_BRK_TIM9_IRQn = 24,
TIM1_UP_TIM10_IRQn = 25,
TIM1_TRG_COM_TIM11_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
TIM4_IRQn = 30,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
I2C2_EV_IRQn = 33,
I2C2_ER_IRQn = 34,
SPI1_IRQn = 35,
SPI2_IRQn = 36,
USART1_IRQn = 37,
USART2_IRQn = 38,
USART3_IRQn = 39,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
USBWakeUp_IRQn = 42,
TIM8_BRK_TIM12_IRQn = 43,
TIM8_UP_TIM13_IRQn = 44,
TIM8_TRG_COM_TIM14_IRQn = 45,
TIM8_CC_IRQn = 46,
ADC3_IRQn = 47,
FSMC_IRQn = 48,
SDIO_IRQn = 49,
TIM5_IRQn = 50,
SPI3_IRQn = 51,
UART4_IRQn = 52,
UART5_IRQn = 53,
TIM6_IRQn = 54,
TIM7_IRQn = 55,
DMA2_Channel1_IRQn = 56,
DMA2_Channel2_IRQn = 57,
DMA2_Channel3_IRQn = 58,
DMA2_Channel4_5_IRQn = 59
#endif
#ifdef STM32F10X_CL
ADC1_2_IRQn = 18,
CAN1_TX_IRQn = 19,
CAN1_RX0_IRQn = 20,
CAN1_RX1_IRQn = 21,
CAN1_SCE_IRQn = 22,
EXTI9_5_IRQn = 23,
TIM1_BRK_IRQn = 24,
TIM1_UP_IRQn = 25,
TIM1_TRG_COM_IRQn = 26,
TIM1_CC_IRQn = 27,
TIM2_IRQn = 28,
TIM3_IRQn = 29,
TIM4_IRQn = 30,
I2C1_EV_IRQn = 31,
I2C1_ER_IRQn = 32,
I2C2_EV_IRQn = 33,
I2C2_ER_IRQn = 34,
SPI1_IRQn = 35,
SPI2_IRQn = 36,
USART1_IRQn = 37,
USART2_IRQn = 38,
USART3_IRQn = 39,
EXTI15_10_IRQn = 40,
RTCAlarm_IRQn = 41,
OTG_FS_WKUP_IRQn = 42,
TIM5_IRQn = 50,
SPI3_IRQn = 51,
UART4_IRQn = 52,
UART5_IRQn = 53,
TIM6_IRQn = 54,
TIM7_IRQn = 55,
DMA2_Channel1_IRQn = 56,
DMA2_Channel2_IRQn = 57,
DMA2_Channel3_IRQn = 58,
DMA2_Channel4_IRQn = 59,
DMA2_Channel5_IRQn = 60,
ETH_IRQn = 61,
ETH_WKUP_IRQn = 62,
CAN2_TX_IRQn = 63,
CAN2_RX0_IRQn = 64,
CAN2_RX1_IRQn = 65,
CAN2_SCE_IRQn = 66,
OTG_FS_IRQn = 67
#endif
} IRQn_Type;
#include "core_cm3.h"
#include "system_stm32f10x.h"
#include
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32;
typedef const int16_t sc16;
typedef const int8_t sc8;
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32;
typedef __I int16_t vsc16;
typedef __I int8_t vsc8;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32;
typedef const uint16_t uc16;
typedef const uint8_t uc8;
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32;
typedef __I uint16_t vuc16;
typedef __I uint8_t vuc8;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
#define HSE_Value HSE_VALUE
#define HSI_Value HSI_VALUE
typedef struct
{
__IO uint32_t SR;
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t SMPR1;
__IO uint32_t SMPR2;
__IO uint32_t JOFR1;
__IO uint32_t JOFR2;
__IO uint32_t JOFR3;
__IO uint32_t JOFR4;
__IO uint32_t HTR;
__IO uint32_t LTR;
__IO uint32_t SQR1;
__IO uint32_t SQR2;
__IO uint32_t SQR3;
__IO uint32_t JSQR;
__IO uint32_t JDR1;
__IO uint32_t JDR2;
__IO uint32_t JDR3;
__IO uint32_t JDR4;
__IO uint32_t DR;
} ADC_TypeDef;
typedef struct
{
uint32_t RESERVED0;
__IO uint16_t DR1;
uint16_t RESERVED1;
__IO uint16_t DR2;
uint16_t RESERVED2;
__IO uint16_t DR3;
uint16_t RESERVED3;
__IO uint16_t DR4;
uint16_t RESERVED4;
__IO uint16_t DR5;
uint16_t RESERVED5;
__IO uint16_t DR6;
uint16_t RESERVED6;
__IO uint16_t DR7;
uint16_t RESERVED7;
__IO uint16_t DR8;
uint16_t RESERVED8;
__IO uint16_t DR9;
uint16_t RESERVED9;
__IO uint16_t DR10;
uint16_t RESERVED10;
__IO uint16_t RTCCR;
uint16_t RESERVED11;
__IO uint16_t CR;
uint16_t RESERVED12;
__IO uint16_t CSR;
uint16_t RESERVED13[5];
__IO uint16_t DR11;
uint16_t RESERVED14;
__IO uint16_t DR12;
uint16_t RESERVED15;
__IO uint16_t DR13;
uint16_t RESERVED16;
__IO uint16_t DR14;
uint16_t RESERVED17;
__IO uint16_t DR15;
uint16_t RESERVED18;
__IO uint16_t DR16;
uint16_t RESERVED19;
__IO uint16_t DR17;
uint16_t RESERVED20;
__IO uint16_t DR18;
uint16_t RESERVED21;
__IO uint16_t DR19;
uint16_t RESERVED22;
__IO uint16_t DR20;
uint16_t RESERVED23;
__IO uint16_t DR21;
uint16_t RESERVED24;
__IO uint16_t DR22;
uint16_t RESERVED25;
__IO uint16_t DR23;
uint16_t RESERVED26;
__IO uint16_t DR24;
uint16_t RESERVED27;
__IO uint16_t DR25;
uint16_t RESERVED28;
__IO uint16_t DR26;
uint16_t RESERVED29;
__IO uint16_t DR27;
uint16_t RESERVED30;
__IO uint16_t DR28;
uint16_t RESERVED31;
__IO uint16_t DR29;
uint16_t RESERVED32;
__IO uint16_t DR30;
uint16_t RESERVED33;
__IO uint16_t DR31;
uint16_t RESERVED34;
__IO uint16_t DR32;
uint16_t RESERVED35;
__IO uint16_t DR33;
uint16_t RESERVED36;
__IO uint16_t DR34;
uint16_t RESERVED37;
__IO uint16_t DR35;
uint16_t RESERVED38;
__IO uint16_t DR36;
uint16_t RESERVED39;
__IO uint16_t DR37;
uint16_t RESERVED40;
__IO uint16_t DR38;
uint16_t RESERVED41;
__IO uint16_t DR39;
uint16_t RESERVED42;
__IO uint16_t DR40;
uint16_t RESERVED43;
__IO uint16_t DR41;
uint16_t RESERVED44;
__IO uint16_t DR42;
uint16_t RESERVED45;
} BKP_TypeDef;
typedef struct
{
__IO uint32_t TIR;
__IO uint32_t TDTR;
__IO uint32_t TDLR;
__IO uint32_t TDHR;
} CAN_TxMailBox_TypeDef;
typedef struct
{
__IO uint32_t RIR;
__IO uint32_t RDTR;
__IO uint32_t RDLR;
__IO uint32_t RDHR;
} CAN_FIFOMailBox_TypeDef;
typedef struct
{
__IO uint32_t FR1;
__IO uint32_t FR2;
} CAN_FilterRegister_TypeDef;
typedef struct
{
__IO uint32_t MCR;
__IO uint32_t MSR;
__IO uint32_t TSR;
__IO uint32_t RF0R;
__IO uint32_t RF1R;
__IO uint32_t IER;
__IO uint32_t ESR;
__IO uint32_t BTR;
uint32_t RESERVED0[88];
CAN_TxMailBox_TypeDef sTxMailBox[3];
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
uint32_t RESERVED1[12];
__IO uint32_t FMR;
__IO uint32_t FM1R;
uint32_t RESERVED2;
__IO uint32_t FS1R;
uint32_t RESERVED3;
__IO uint32_t FFA1R;
uint32_t RESERVED4;
__IO uint32_t FA1R;
uint32_t RESERVED5[8];
#ifndef STM32F10X_CL
CAN_FilterRegister_TypeDef sFilterRegister[14];
#else
CAN_FilterRegister_TypeDef sFilterRegister[28];
#endif
} CAN_TypeDef;
typedef struct
{
__IO uint32_t CFGR;
__IO uint32_t OAR;
__IO uint32_t PRES;
__IO uint32_t ESR;
__IO uint32_t CSR;
__IO uint32_t TXD;
__IO uint32_t RXD;
} CEC_TypeDef;
typedef struct
{
__IO uint32_t DR;
__IO uint8_t IDR;
uint8_t RESERVED0;
uint16_t RESERVED1;
__IO uint32_t CR;
} CRC_TypeDef;
typedef struct
{
__IO uint32_t CR;
__IO uint32_t SWTRIGR;
__IO uint32_t DHR12R1;
__IO uint32_t DHR12L1;
__IO uint32_t DHR8R1;
__IO uint32_t DHR12R2;
__IO uint32_t DHR12L2;
__IO uint32_t DHR8R2;
__IO uint32_t DHR12RD;
__IO uint32_t DHR12LD;
__IO uint32_t DHR8RD;
__IO uint32_t DOR1;
__IO uint32_t DOR2;
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
__IO uint32_t SR;
#endif
} DAC_TypeDef;
typedef struct
{
__IO uint32_t IDCODE;
__IO uint32_t CR;
}DBGMCU_TypeDef;
typedef struct
{
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR;
__IO uint32_t IFCR;
} DMA_TypeDef;
typedef struct
{
__IO uint32_t MACCR;
__IO uint32_t MACFFR;
__IO uint32_t MACHTHR;
__IO uint32_t MACHTLR;
__IO uint32_t MACMIIAR;
__IO uint32_t MACMIIDR;
__IO uint32_t MACFCR;
__IO uint32_t MACVLANTR;
uint32_t RESERVED0[2];
__IO uint32_t MACRWUFFR;
__IO uint32_t MACPMTCSR;
uint32_t RESERVED1[2];
__IO uint32_t MACSR;
__IO uint32_t MACIMR;
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR;
uint32_t RESERVED2[40];
__IO uint32_t MMCCR;
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR;
uint32_t RESERVED3[14];
__IO uint32_t MMCTGFSCCR;
__IO uint32_t MMCTGFMSCCR;
uint32_t RESERVED4[5];
__IO uint32_t MMCTGFCR;
uint32_t RESERVED5[10];
__IO uint32_t MMCRFCECR;
__IO uint32_t MMCRFAECR;
uint32_t RESERVED6[10];
__IO uint32_t MMCRGUFCR;
uint32_t RESERVED7[334];
__IO uint32_t PTPTSCR;
__IO uint32_t PTPSSIR;
__IO uint32_t PTPTSHR;
__IO uint32_t PTPTSLR;
__IO uint32_t PTPTSHUR;
__IO uint32_t PTPTSLUR;
__IO uint32_t PTPTSAR;
__IO uint32_t PTPTTHR;
__IO uint32_t PTPTTLR;
uint32_t RESERVED8[567];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
__IO uint32_t DMARDLAR;
__IO uint32_t DMATDLAR;
__IO uint32_t DMASR;
__IO uint32_t DMAOMR;
__IO uint32_t DMAIER;
__IO uint32_t DMAMFBOCR;
uint32_t RESERVED9[9];
__IO uint32_t DMACHTDR;
__IO uint32_t DMACHRDR;
__IO uint32_t DMACHTBAR;
__IO uint32_t DMACHRBAR;
} ETH_TypeDef;
typedef struct
{
__IO uint32_t IMR;
__IO uint32_t EMR;
__IO uint32_t RTSR;
__IO uint32_t FTSR;
__IO uint32_t SWIER;
__IO uint32_t PR;
} EXTI_TypeDef;
typedef struct
{
__IO uint32_t ACR;
__IO uint32_t KEYR;
__IO uint32_t OPTKEYR;
__IO uint32_t SR;
__IO uint32_t CR;
__IO uint32_t AR;
__IO uint32_t RESERVED;
__IO uint32_t OBR;
__IO uint32_t WRPR;
#ifdef STM32F10X_XL
uint32_t RESERVED1[8];
__IO uint32_t KEYR2;
uint32_t RESERVED2;
__IO uint32_t SR2;
__IO uint32_t CR2;
__IO uint32_t AR2;
#endif
} FLASH_TypeDef;
typedef struct
{
__IO uint16_t RDP;
__IO uint16_t USER;
__IO uint16_t Data0;
__IO uint16_t Data1;
__IO uint16_t WRP0;
__IO uint16_t WRP1;
__IO uint16_t WRP2;
__IO uint16_t WRP3;
} OB_TypeDef;
typedef struct
{
__IO uint32_t BTCR[8];
} FSMC_Bank1_TypeDef;
typedef struct
{
__IO uint32_t BWTR[7];
} FSMC_Bank1E_TypeDef;
typedef struct
{
__IO uint32_t PCR2;
__IO uint32_t SR2;
__IO uint32_t PMEM2;
__IO uint32_t PATT2;
uint32_t RESERVED0;
__IO uint32_t ECCR2;
} FSMC_Bank2_TypeDef;
typedef struct
{
__IO uint32_t PCR3;
__IO uint32_t SR3;
__IO uint32_t PMEM3;
__IO uint32_t PATT3;
uint32_t RESERVED0;
__IO uint32_t ECCR3;
} FSMC_Bank3_TypeDef;
typedef struct
{
__IO uint32_t PCR4;
__IO uint32_t SR4;
__IO uint32_t PMEM4;
__IO uint32_t PATT4;
__IO uint32_t PIO4;
} FSMC_Bank4_TypeDef;
typedef struct
{
__IO uint32_t CRL;
__IO uint32_t CRH;
__IO uint32_t IDR;
__IO uint32_t ODR;
__IO uint32_t BSRR;
__IO uint32_t BRR;
__IO uint32_t LCKR;
} GPIO_TypeDef;
typedef struct
{
__IO uint32_t EVCR;
__IO uint32_t MAPR;
__IO uint32_t EXTICR[4];
uint32_t RESERVED0;
__IO uint32_t MAPR2;
} AFIO_TypeDef;
typedef struct
{
__IO uint16_t CR1;
uint16_t RESERVED0;
__IO uint16_t CR2;
uint16_t RESERVED1;
__IO uint16_t OAR1;
uint16_t RESERVED2;
__IO uint16_t OAR2;
uint16_t RESERVED3;
__IO uint16_t DR;
uint16_t RESERVED4;
__IO uint16_t SR1;
uint16_t RESERVED5;
__IO uint16_t SR2;
uint16_t RESERVED6;
__IO uint16_t CCR;
uint16_t RESERVED7;
__IO uint16_t TRISE;
uint16_t RESERVED8;
} I2C_TypeDef;
typedef struct
{
__IO uint32_t KR;
__IO uint32_t PR;
__IO uint32_t RLR;
__IO uint32_t SR;
} IWDG_TypeDef;
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CSR;
} PWR_TypeDef;
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CFGR;
__IO uint32_t CIR;
__IO uint32_t APB2RSTR;
__IO uint32_t APB1RSTR;
__IO uint32_t AHBENR;
__IO uint32_t APB2ENR;
__IO uint32_t APB1ENR;
__IO uint32_t BDCR;
__IO uint32_t CSR;
#ifdef STM32F10X_CL
__IO uint32_t AHBRSTR;
__IO uint32_t CFGR2;
#endif
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
uint32_t RESERVED0;
__IO uint32_t CFGR2;
#endif
} RCC_TypeDef;
typedef struct
{
__IO uint16_t CRH;
uint16_t RESERVED0;
__IO uint16_t CRL;
uint16_t RESERVED1;
__IO uint16_t PRLH;
uint16_t RESERVED2;
__IO uint16_t PRLL;
uint16_t RESERVED3;
__IO uint16_t DIVH;
uint16_t RESERVED4;
__IO uint16_t DIVL;
uint16_t RESERVED5;
__IO uint16_t CNTH;
uint16_t RESERVED6;
__IO uint16_t CNTL;
uint16_t RESERVED7;
__IO uint16_t ALRH;
uint16_t RESERVED8;
__IO uint16_t ALRL;
uint16_t RESERVED9;
} RTC_TypeDef;
typedef struct
{
__IO uint32_t POWER;
__IO uint32_t CLKCR;
__IO uint32_t ARG;
__IO uint32_t CMD;
__I uint32_t RESPCMD;
__I uint32_t RESP1;
__I uint32_t RESP2;
__I uint32_t RESP3;
__I uint32_t RESP4;
__IO uint32_t DTIMER;
__IO uint32_t DLEN;
__IO uint32_t DCTRL;
__I uint32_t DCOUNT;
__I uint32_t STA;
__IO uint32_t ICR;
__IO uint32_t MASK;
uint32_t RESERVED0[2];
__I uint32_t FIFOCNT;
uint32_t RESERVED1[13];
__IO uint32_t FIFO;
} SDIO_TypeDef;
typedef struct
{
__IO uint16_t CR1;
uint16_t RESERVED0;
__IO uint16_t CR2;
uint16_t RESERVED1;
__IO uint16_t SR;
uint16_t RESERVED2;
__IO uint16_t DR;
uint16_t RESERVED3;
__IO uint16_t CRCPR;
uint16_t RESERVED4;
__IO uint16_t RXCRCR;
uint16_t RESERVED5;
__IO uint16_t TXCRCR;
uint16_t RESERVED6;
__IO uint16_t I2SCFGR;
uint16_t RESERVED7;
__IO uint16_t I2SPR;
uint16_t RESERVED8;
} SPI_TypeDef;
typedef struct
{
__IO uint16_t CR1;
uint16_t RESERVED0;
__IO uint16_t CR2;
uint16_t RESERVED1;
__IO uint16_t SMCR;
uint16_t RESERVED2;
__IO uint16_t DIER;
uint16_t RESERVED3;
__IO uint16_t SR;
uint16_t RESERVED4;
__IO uint16_t EGR;
uint16_t RESERVED5;
__IO uint16_t CCMR1;
uint16_t RESERVED6;
__IO uint16_t CCMR2;
uint16_t RESERVED7;
__IO uint16_t CCER;
uint16_t RESERVED8;
__IO uint16_t CNT;
uint16_t RESERVED9;
__IO uint16_t PSC;
uint16_t RESERVED10;
__IO uint16_t ARR;
uint16_t RESERVED11;
__IO uint16_t RCR;
uint16_t RESERVED12;
__IO uint16_t CCR1;
uint16_t RESERVED13;
__IO uint16_t CCR2;
uint16_t RESERVED14;
__IO uint16_t CCR3;
uint16_t RESERVED15;
__IO uint16_t CCR4;
uint16_t RESERVED16;
__IO uint16_t BDTR;
uint16_t RESERVED17;
__IO uint16_t DCR;
uint16_t RESERVED18;
__IO uint16_t DMAR;
uint16_t RESERVED19;
} TIM_TypeDef;
typedef struct
{
__IO uint16_t SR;
uint16_t RESERVED0;
__IO uint16_t DR;
uint16_t RESERVED1;
__IO uint16_t BRR;
uint16_t RESERVED2;
__IO uint16_t CR1;
uint16_t RESERVED3;
__IO uint16_t CR2;
uint16_t RESERVED4;
__IO uint16_t CR3;
uint16_t RESERVED5;
__IO uint16_t GTPR;
uint16_t RESERVED6;
} USART_TypeDef;
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CFR;
__IO uint32_t SR;
} WWDG_TypeDef;
#define FLASH_BASE ((uint32_t)0x08000000)
#define SRAM_BASE ((uint32_t)0x20000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define SRAM_BB_BASE ((uint32_t)0x22000000)
#define PERIPH_BB_BASE ((uint32_t)0x42000000)
#define FSMC_R_BASE ((uint32_t)0xA0000000)
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
#define SDIO_BASE (PERIPH_BASE + 0x18000)
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
#define OB_BASE ((uint32_t)0x1FFFF800)
#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
#define ETH_MAC_BASE (ETH_BASE)
#define ETH_MMC_BASE (ETH_BASE + 0x0100)
#define ETH_PTP_BASE (ETH_BASE + 0x0700)
#define ETH_DMA_BASE (ETH_BASE + 0x1000)
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
#define DBGMCU_BASE ((uint32_t)0xE0042000)
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define BKP ((BKP_TypeDef *) BKP_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define CEC ((CEC_TypeDef *) CEC_BASE)
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF)
#define CRC_IDR_IDR ((uint8_t)0xFF)
#define CRC_CR_RESET ((uint8_t)0x01)
#define PWR_CR_LPDS ((uint16_t)0x0001)
#define PWR_CR_PDDS ((uint16_t)0x0002)
#define PWR_CR_CWUF ((uint16_t)0x0004)
#define PWR_CR_CSBF ((uint16_t)0x0008)
#define PWR_CR_PVDE ((uint16_t)0x0010)
#define PWR_CR_PLS ((uint16_t)0x00E0)
#define PWR_CR_PLS_0 ((uint16_t)0x0020)
#define PWR_CR_PLS_1 ((uint16_t)0x0040)
#define PWR_CR_PLS_2 ((uint16_t)0x0080)
#define PWR_CR_PLS_2V2 ((uint16_t)0x0000)
#define PWR_CR_PLS_2V3 ((uint16_t)0x0020)
#define PWR_CR_PLS_2V4 ((uint16_t)0x0040)
#define PWR_CR_PLS_2V5 ((uint16_t)0x0060)
#define PWR_CR_PLS_2V6 ((uint16_t)0x0080)
#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0)
#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0)
#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0)
#define PWR_CR_DBP ((uint16_t)0x0100)
#define PWR_CSR_WUF ((uint16_t)0x0001)
#define PWR_CSR_SBF ((uint16_t)0x0002)
#define PWR_CSR_PVDO ((uint16_t)0x0004)
#define PWR_CSR_EWUP ((uint16_t)0x0100)
#define BKP_DR1_D ((uint16_t)0xFFFF)
#define BKP_DR2_D ((uint16_t)0xFFFF)
#define BKP_DR3_D ((uint16_t)0xFFFF)
#define BKP_DR4_D ((uint16_t)0xFFFF)
#define BKP_DR5_D ((uint16_t)0xFFFF)
#define BKP_DR6_D ((uint16_t)0xFFFF)
#define BKP_DR7_D ((uint16_t)0xFFFF)
#define BKP_DR8_D ((uint16_t)0xFFFF)
#define BKP_DR9_D ((uint16_t)0xFFFF)
#define BKP_DR10_D ((uint16_t)0xFFFF)
#define BKP_DR11_D ((uint16_t)0xFFFF)
#define BKP_DR12_D ((uint16_t)0xFFFF)
#define BKP_DR13_D ((uint16_t)0xFFFF)
#define BKP_DR14_D ((uint16_t)0xFFFF)
#define BKP_DR15_D ((uint16_t)0xFFFF)
#define BKP_DR16_D ((uint16_t)0xFFFF)
#define BKP_DR17_D ((uint16_t)0xFFFF)
#define BKP_DR18_D ((uint16_t)0xFFFF)
#define BKP_DR19_D ((uint16_t)0xFFFF)
#define BKP_DR20_D ((uint16_t)0xFFFF)
#define BKP_DR21_D ((uint16_t)0xFFFF)
#define BKP_DR22_D ((uint16_t)0xFFFF)
#define BKP_DR23_D ((uint16_t)0xFFFF)
#define BKP_DR24_D ((uint16_t)0xFFFF)
#define BKP_DR25_D ((uint16_t)0xFFFF)
#define BKP_DR26_D ((uint16_t)0xFFFF)
#define BKP_DR27_D ((uint16_t)0xFFFF)
#define BKP_DR28_D ((uint16_t)0xFFFF)
#define BKP_DR29_D ((uint16_t)0xFFFF)
#define BKP_DR30_D ((uint16_t)0xFFFF)
#define BKP_DR31_D ((uint16_t)0xFFFF)
#define BKP_DR32_D ((uint16_t)0xFFFF)
#define BKP_DR33_D ((uint16_t)0xFFFF)
#define BKP_DR34_D ((uint16_t)0xFFFF)
#define BKP_DR35_D ((uint16_t)0xFFFF)
#define BKP_DR36_D ((uint16_t)0xFFFF)
#define BKP_DR37_D ((uint16_t)0xFFFF)
#define BKP_DR38_D ((uint16_t)0xFFFF)
#define BKP_DR39_D ((uint16_t)0xFFFF)
#define BKP_DR40_D ((uint16_t)0xFFFF)
#define BKP_DR41_D ((uint16_t)0xFFFF)
#define BKP_DR42_D ((uint16_t)0xFFFF)
#define BKP_RTCCR_CAL ((uint16_t)0x007F)
#define BKP_RTCCR_CCO ((uint16_t)0x0080)
#define BKP_RTCCR_ASOE ((uint16_t)0x0100)
#define BKP_RTCCR_ASOS ((uint16_t)0x0200)
#define BKP_CR_TPE ((uint8_t)0x01)
#define BKP_CR_TPAL ((uint8_t)0x02)
#define BKP_CSR_CTE ((uint16_t)0x0001)
#define BKP_CSR_CTI ((uint16_t)0x0002)
#define BKP_CSR_TPIE ((uint16_t)0x0004)
#define BKP_CSR_TEF ((uint16_t)0x0100)
#define BKP_CSR_TIF ((uint16_t)0x0200)
#define RCC_CR_HSION ((uint32_t)0x00000001)
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
#define RCC_CR_HSEON ((uint32_t)0x00010000)
#define RCC_CR_HSERDY ((uint32_t)0x00020000)
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define RCC_CR_CSSON ((uint32_t)0x00080000)
#define RCC_CR_PLLON ((uint32_t)0x01000000)
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
#ifdef STM32F10X_CL
#define RCC_CR_PLL2ON ((uint32_t)0x04000000)
#define RCC_CR_PLL2RDY ((uint32_t)0x08000000)
#define RCC_CR_PLL3ON ((uint32_t)0x10000000)
#define RCC_CR_PLL3RDY ((uint32_t)0x20000000)
#endif
#define RCC_CFGR_SW ((uint32_t)0x00000003)
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001)
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002)
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000)
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001)
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002)
#define RCC_CFGR_SWS ((uint32_t)0x0000000C)
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0)
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700)
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100)
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200)
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400)
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400)
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500)
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600)
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700)
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800)
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800)
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000)
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000)
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000)
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800)
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000)
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800)
#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000)
#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000)
#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000)
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)
#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000)
#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000)
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000)
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000)
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000)
#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000)
#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000)
#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000)
#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000)
#ifdef STM32F10X_CL
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000)
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000)
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000)
#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000)
#define RCC_CFGR_MCO ((uint32_t)0x0F000000)
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000)
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000)
#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000)
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000)
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000)
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000)
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000)
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000)
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
#define RCC_CFGR_MCO ((uint32_t)0x07000000)
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
#else
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000)
#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000)
#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000)
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000)
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000)
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000)
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000)
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000)
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000)
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000)
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000)
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000)
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000)
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000)
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000)
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000)
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000)
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000)
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000)
#define RCC_CFGR_MCO ((uint32_t)0x07000000)
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000)
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000)
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000)
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000)
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000)
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000)
#endif
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define RCC_CIR_CSSC ((uint32_t)0x00800000)
#ifdef STM32F10X_CL
#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020)
#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040)
#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000)
#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000)
#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000)
#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000)
#endif
#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001)
#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004)
#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008)
#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010)
#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020)
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200)
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400)
#endif
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000)
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000)
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000)
#endif
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080)
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100)
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000)
#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000)
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080)
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100)
#endif
#ifdef STM32F10X_XL
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000)
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000)
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000)
#endif
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
#endif
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000)
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
#endif
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000)
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#endif
#ifdef STM32F10X_CL
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
#endif
#ifdef STM32F10X_XL
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
#endif
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001)
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004)
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010)
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040)
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100)
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400)
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100)
#endif
#ifdef STM32F10X_CL
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000)
#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000)
#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000)
#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000)
#endif
#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001)
#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004)
#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008)
#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010)
#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020)
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200)
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400)
#endif
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000)
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000)
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000)
#endif
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080)
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100)
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000)
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000)
#endif
#if defined (STM32F10X_HD_VL)
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080)
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100)
#endif
#ifdef STM32F10X_XL
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000)
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000)
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000)
#endif
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
#endif
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000)
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000)
#endif
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
#endif
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000)
#endif
#ifdef STM32F10X_HD_VL
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#endif
#ifdef STM32F10X_CL
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
#endif
#ifdef STM32F10X_XL
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
#endif
#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000)
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100)
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200)
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300)
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
#define RCC_CSR_LSION ((uint32_t)0x00000001)
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define RCC_CSR_RMVF ((uint32_t)0x01000000)
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
#ifdef STM32F10X_CL
#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000)
#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000)
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F)
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001)
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002)
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004)
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008)
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000)
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001)
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002)
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003)
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004)
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005)
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006)
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007)
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008)
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009)
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A)
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B)
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C)
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D)
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E)
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F)
#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0)
#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010)
#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020)
#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040)
#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080)
#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000)
#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010)
#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020)
#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030)
#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040)
#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050)
#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060)
#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070)
#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080)
#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090)
#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0)
#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0)
#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0)
#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0)
#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0)
#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0)
#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00)
#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100)
#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200)
#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400)
#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800)
#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600)
#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700)
#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800)
#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900)
#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00)
#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00)
#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00)
#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00)
#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00)
#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000)
#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000)
#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000)
#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000)
#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000)
#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000)
#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000)
#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000)
#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000)
#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000)
#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000)
#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000)
#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000)
#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000)
#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000)
#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000)
#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000)
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000)
#endif
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F)
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001)
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002)
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004)
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008)
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000)
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001)
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002)
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003)
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004)
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005)
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006)
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007)
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008)
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009)
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A)
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B)
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C)
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D)
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E)
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F)
#endif

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