标题: JTAG时钟导致的DM648网口异常 [打印本页] 作者: 51黑专家 时间: 2016-4-15 03:29 标题: JTAG时钟导致的DM648网口异常 今天看到了个帖子，关于DM648网口异常的。最终原因是JTAG的TCLK没有下拉导致。下面是原帖部分内容：
We've been having problems with Ethernet comms on our custom board……
The root of the problem is the need for a pull down on the TCK pin, as per TI Advisory note 1.1.4. I added this and the port started to behave itself instantly.
在网上搜到相关的注释及说明：
因为JTAG的TCLK与网络部分的STCICLK共用，STCICLK需要默认下拉，而该引脚在DSP内部默认上拉，所以会导致网络模块异常。
Figure Workaround Example
Advisory 1.1.4
Revision(s) Affected Details
3-Port Ethernet Switch Subsystem (3PSW) clocking problem normal functional operation earlier (JTAG controller clock) internally shared 3-Port Ethernet Switch Subsystem's (3PSW) STCICLK test debug mode. order 3-Port Ethernet Switch Subsystem (3PSW) proper clocking normal functional operation, STCICLK needs held low. since there internal pullup TCK, keeps 3-Port Ethernet Switch Subsystem from locking external REFCLKP/N proper operation. should externally pulled down with resistor.