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基于FPGA的3位锁存
- Ilibrsry ieee;
- use ieee.std_logic_1164.all;
- entity sn74373 is
- port(d: in std_logic_vetor(8 downto 1);
- OEN:in std_logic;
- G:in std_logic;
- Q:out std_logic_vector(8 downto 1));
- end entity sn74373;
- architecture two of sn74373 is
- signal sigvec_save:std_logic_vector(8 downto 1);
- begin
- process(D,OEN,G)
- begin
- if OEN='0' then
- Q<=sigvec_save;
- else
- Q<="ZZZZZZZZ";
- end if;
- if G='1' then
- sigvec_save<=D;
- end if;
- end process;
- eng architecture two;
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fpga.docx
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3位所存
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