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第一帖
Figure 2 illustrates the functional modules in this demo design. The PCS receives DVI/SDI serial video
steam and converts it into parallel video data. Then after the decoder of DVI/SDI IP, the two video
streams and the corresponding synchronous signals on the two video channels are selected from the
four video sources and connected with the video processing IPs. It can be seen from the diagram that
there are two identical data paths for the video processing on the two video channels. The on board
DDR3 memories are used for the de‐interlacer IP and the frame buffer IP. Finally the two video
steams will be combined into one picture with OSD and transmitted to the DVI and SDI interface.
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