VHDL错误:Warning: ELAB1_0026:x: There is no default binding for component

调用的时候一直Warning: ELAB1_0026: register_8_1.vhd : (48, 0): There is no default binding for component "dff". (Port "A" is not on the entity).
如果改用位置调用会报错：代码如下：library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;
entity register_8 is
  port(
   clk,clr,A: in STD_LOGIC;
   Z : out STD_LOGIC_VECTOR(7 downto 0)
      );
end register_8;
--}} End of automatically maintained section
architecture rtl of register_8 is
component dff
port(clk,clr,A:in STD_LOGIC;
Z : out STD_LOGIC);
end component;

signal s:STD_LOGIC_VECTOR(8 downto 0);
begin
  s(0)<=A;
  gl:for i IN 0 to 8 generate
   dffx:dff port map(clk=>clk,clr=>clr,s(i)=>d,s(i+1)=>q);
  end generate;
Z<=s(8 downto 1);
end rtl;
报错如下：
# Error: COMP96_0078: register_8_1.vhd : (48, 46): Unknown identifier "d".
# Error: COMP96_0078: register_8_1.vhd : (48, 56): Unknown identifier "q".
# Error: COMP96_0078: register_8_1.vhd : (48, 40): Unknown identifier "s".
# Error: COMP96_0078: register_8_1.vhd : (48, 48): Unknown identifier "s".
# Error: COMP96_0112: register_8_1.vhd : (48, 40): "s" does not match the formal name.
# Error: COMP96_0207: register_8_1.vhd : (48, 0): No actual specified for local port "A".

问题出在哪里，解决了吗？