VHDL语句的四选一结构描述
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity erxuanyi is
Port ( A, B, Sel : in std_logic;
Y : out std_logic);
end erxuanyi;
architecture Behavioral of erxuanyi is
begin
Y <= A when Sel = '0' else B;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sixuanyi is
Port ( A, B, C, D, Sel : in std_logic_vector(1 downto 0);
Y : out std_logic);
end sixuanyi;
-- 实现模块
architecture Behavioral of sixuanyi is
-- 元件例化
component erxuanyi
Port ( A, B, Sel : in std_logic;
Y : out std_logic);
end component;
-- 信号定义
signal AB, CD : std_logic;
begin
-- 实例化二选一模块
U1: erxuanyi port map (A => A(0), B => B(0), Sel => Sel(0), Y => AB);
U2: erxuanyi port map (A => C(0), B => D(0), Sel => Sel(0), Y => CD);
-- 连接选择信号
U3: erxuanyi port map (A => AB, B => CD, Sel => Sel(1), Y => Y);
end Behavioral;
verilog语句的四选一结构描述
module erxuanyi(
input A, B, Sel,
output Y
);
assign Y = (Sel == 1'b0) ? A : B;
endmodule
module sixuanyi(
input [1:0] A, B, C, D, Sel,
output Y
);
wire AB, CD;
erxuanyi U1(
.A(A[0]), .B(B[0]), .Sel(Sel[0]),
.Y(AB)
);
erxuanyi U2(
.A(C[0]), .B(D[0]), .Sel(Sel[0]),
.Y(CD)
);
erxuanyi U3(
.A(AB), .B(CD), .Sel(Sel[1]),
.Y(Y)
);
endmodule
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