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CC1101 MSP430收发程序

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ID:438785 发表于 2018-12-5 18:13 | 显示全部楼层 |阅读模式
  1. #include "msp430g2452.h"
  2. #include "common.h"
  3. #include "regssrf04.h"
  4. #include "initial_spi.h"
  5. #include "Uart9600.h"
  6. #define CRC_OK              0x80  
  7. #define RSSI                0
  8. #define LQI                 1
  9. #define BYTES_IN_RXFIFO     0x7F   

  11. #define sys_in     P2OUT|=BIT3;
  12. #define com_on     P2OUT|=BIT4;
  13. #define com_off    P2OUT&=~BIT4;
  14. #define sys_0ff    P2OUT&=~BIT3;

  16. BYTE rxBuffer[61];
  17. BYTE txBuffer[10]={0x80,0x00,0x00,0x00,0x00,0x90,0x00,0x50,0x50,0x50};
  18. void halRfWriteRfSettings(/*const RF_SETTINGS *pRfSettings*/);
  19. void halRfSendPacket(BYTE *txBuffer, UINT8 size) ;
  20. void interrupt_initial();
  21. void delay_tx();
  22. unsigned char tx_ready=0;
  23. unsigned char length;
  24. unsigned char count=0;
  25. void systime_initial(void)
  26. {
  27. WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
  28. DCOCTL =CALDCO_1MHZ;
  29. BCSCTL1 = CALBC1_1MHZ;
  30. __enable_interrupt();
  31. }
  32. void IO_initial(void)
  33. {
  34. //********************************************************
  35. //SPI端口初始化
  36. //********************************************************
  37.         SI_OUTPUT ;
  38.         SO_INPUT ;
  39.         CSN_OUTPUT;
  40.         SCLK_OUTPUT;

  42.         P2DIR|=BIT3+BIT4;               //系统，通信指示灯      
  43. //**************************************************************
  44. //串口初始化，模拟的
  45. //******************************************************************
  46.         P1SEL = UART_TXD + UART_RXD;    // 串口，Timer function for TXD/RXD pins
  47.         P1DIR|=UART_TXD;
  48. //******************************************************************
  49. }
  50. //******************************************************************
  51. //***中断初始化
  52. //*****************************************************************
  53. void halRfWriteRfSettings()
  54. {
  55.     // Write register settings
  56.     SPI_WriteReg(CCxxx0_FSCTRL1,  0x06);// FSCTRL1   Frequency synthesizer control.
  57.     SPI_WriteReg(CCxxx0_FSCTRL0,  0x00);// FSCTRL0   Frequency synthesizer control.
  58.     SPI_WriteReg(CCxxx0_FREQ2,    0x10);// FREQ2     Frequency control word, high byte.
  59.     SPI_WriteReg(CCxxx0_FREQ1,    0xB1);// FREQ1     Frequency control word, middle byte.
  60.     SPI_WriteReg(CCxxx0_FREQ0,    0x3B);// FREQ0     Frequency control word, low byte.
  61.     SPI_WriteReg(CCxxx0_MDMCFG4,  0xF6);// MDMCFG4   Modem configuration.
  62.     SPI_WriteReg(CCxxx0_MDMCFG3,  0x83);// MDMCFG3   Modem configuration.
  63.     SPI_WriteReg(CCxxx0_MDMCFG2,  0x13);// MDMCFG2   Modem configuration.
  64.     SPI_WriteReg(CCxxx0_MDMCFG1,  0x22);// MDMCFG1   Modem configuration.
  65.     SPI_WriteReg(CCxxx0_MDMCFG0,  0xF8);// MDMCFG0   Modem configuration.
  66.     SPI_WriteReg(CCxxx0_CHANNR,   0x00);// CHANNR    Channel number.
  67.     SPI_WriteReg(CCxxx0_DEVIATN,  0x15);// DEVIATN   Modem deviation setting (when FSK modulation is enabled).
  68.     SPI_WriteReg(CCxxx0_FREND1,   0x56);// FREND1    Front end RX configuration.
  69.     SPI_WriteReg(CCxxx0_FREND0,   0x10);// FREND0    Front end TX configuration.
  70.     SPI_WriteReg(CCxxx0_MCSM0 ,   0x18);// MCSM0     Main Radio Control State Machine configuration.
  71.     SPI_WriteReg(CCxxx0_FOCCFG,   0x16);// FOCCFG    Frequency Offset Compensation Configuration.
  72.     SPI_WriteReg(CCxxx0_BSCFG,    0x6C);// BSCFG     Bit synchronization Configuration.
  73.     SPI_WriteReg(CCxxx0_AGCCTRL2, 0x03);// AGCCTRL2  AGC control.
  74.     SPI_WriteReg(CCxxx0_AGCCTRL1, 0x40);// AGCCTRL1  AGC control.
  75.     SPI_WriteReg(CCxxx0_AGCCTRL0, 0x91);// AGCCTRL0  AGC control.
  76.     SPI_WriteReg(CCxxx0_FSCAL3,   0xE9);// FSCAL3    Frequency synthesizer calibration.
  77.     SPI_WriteReg(CCxxx0_FSCAL2,   0x2A);// FSCAL2    Frequency synthesizer calibration.
  78.     SPI_WriteReg(CCxxx0_FSCAL1,   0x00);// FSCAL1    Frequency synthesizer calibration.
  79.     SPI_WriteReg(CCxxx0_FSCAL0,   0x1F);// FSCAL0    Frequency synthesizer calibration.
  80.     SPI_WriteReg(CCxxx0_FSTEST,   0x59);// FSTEST    Frequency synthesizer calibration.
  81.     SPI_WriteReg(CCxxx0_TEST2,    0x81);// TEST2     Various test settings.
  82.     SPI_WriteReg(CCxxx0_TEST1,    0x35);// TEST1     Various test settings.
  83.     SPI_WriteReg(CCxxx0_TEST0,    0x09);// TEST0     Various test settings.
  84.     SPI_WriteReg(CCxxx0_FIFOTHR,  0x47);// FIFOTHR   RXFIFO and TXFIFO thresholds.
  85.     SPI_WriteReg(CCxxx0_IOCFG2,   0x2e);// IOCFG2    GDO2 output pin configuration.
  86.     SPI_WriteReg(CCxxx0_IOCFG0,   0x06);// IOCFG0D   GDO0 output pin configuration.
  87.     SPI_WriteReg(CCxxx0_PKTCTRL1, 0x04);// PKTCTRL1  Packet automation control.
  88.     SPI_WriteReg(CCxxx0_PKTCTRL0, 0x05);// PKTCTRL0  Packet automation control.
  89.     SPI_WriteReg(CCxxx0_ADDR,     0x00);// ADDR      Device address.
  90.     SPI_WriteReg(CCxxx0_PKTLEN,   0xFF);// PKTLEN    Packet length.
  91. }

  93. void interrupt_initial()
  94. {
  95.         WDTCTL = WDT_MDLY_32;                     // Set Watchdog Timer interval to ~30ms
  96.         IE1 |= WDTIE;                             // Enable WDT interrupt
  97. }

  99. #pragma vector=WDT_VECTOR
  100. __interrupt void watchdog_timer(void)
  101. {
  102.         count=count+1;
  103.         if(count>250)
  104.         {
  105.           count=0;
  106.           SPI_Strobe(CCxxx0_SIDLE  );
  107.       halRfSendPacket(txBuffer, 10);
  108.          // com_on;
  109.           __delay_cycles(10000);
  110.           __delay_cycles(10000);
  111.          SPI_Strobe(CCxxx0_SPWD);
  112.          _bis_SR_register(LPM4_bits);
  113.         }
  114. }


  117. BYTE  halRfReceivePacket(BYTE *rxBuffer, UINT8 *length)
  118. {
  119.     BYTE status[2];
  120.     unsigned char packetLength;
  121.     unsigned char  DATE;
  122.     SPI_Strobe(CCxxx0_SRX);
  123.    // Wait for GDO0 to be set -> sync received
  124.      while (!GDO0_PIN);
  125.     // Wait for GDO0 to be cleared -> end of packet
  126.      while (GDO0_PIN);
  127.     DATE=SPI_ReadStatus(CCxxx0_RXBYTES);
  128.     // This status register is safe to read since it will not be updated after
  129.     // the packet has been received (See the CC1100 and 2500 Errata Note)
  130.     if (( DATE& BYTES_IN_RXFIFO))
  131.         {
  132.         // Read length byte
  133.         packetLength = SPI_ReadReg(CCxxx0_RXFIFO);
  134.         // Read data from RX FIFO and store in rxBuffer
  135.         if (packetLength <= *length)
  136.         {
  137.            SPI_ReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength);
  138.            *length = packetLength;
  139.             // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
  140.            SPI_ReadBurstReg(CCxxx0_RXFIFO, status, 2);
  141.             // MSB of LQI is the CRC_OK bit
  142.            return (status[LQI] & CRC_OK);

  144.         }
  145.         else
  146.         {
  147.             *length = packetLength;
  148.             // Make sure that the radio is in IDLE state before flushing the FIFO
  149.             // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
  150.             SPI_Strobe(CCxxx0_SIDLE);
  151.             // Flush RX FIFO
  152.             SPI_Strobe(CCxxx0_SFRX);
  153.             return FALSE;
  154.          
  155.         }
  156.     }
  157.     else
  158.     {
  159.         return FALSE;
  160.         
  161.     }
  162.    
  163. }// halRfReceivePacket

  165. void halRfSendPacket(BYTE *txBuffer, UINT8 size)
  166. {
  167.         SPI_WriteReg(CCxxx0_TXFIFO ,size);
  168.         SPI_WriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
  169.         SPI_Strobe(CCxxx0_STX);
  170.     // Wait for GDO0 to be set -> sync received
  171.     while (!GDO0_PIN);
  172.     // Wait for GDO0 to be cleared -> end of packet
  173.     while (GDO0_PIN);
  174.     SPI_Strobe(CCxxx0_SFTX);
  175. }


  178. void main(void)
  179. {
  180. //unsigned char m;
  181. systime_initial();
  182. IO_initial();
  183. interrupt_initial();
  184. TimerA_UART_init();
  185. SPI_Strobe(CCxxx0_SRES);
  186. halRfWriteRfSettings(/*&rfSettings*/ );
  187.   __delay_cycles(10000);
  188. sys_0ff;                            //系统启动指示灯亮
  189. while(1)
  190. {
  191.          com_off;
  192. }
  193. }
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ID:223999 发表于 2019-3-6 10:58 | 显示全部楼层
听所长时间接收会死机
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