用verilog语言实现ego1的篮球计分器代码修改问题

ID:558025 · 发表于 2019-6-9 10:31

这是之前的源程序

但是硬件改为了ego1

里面的约束条件和解码是不是要改

怎么改？

希望可以把拨码开关换成按键的

要求给出改完之后的源程序和源文件。

1.Verilog程序：

moduleshumaguan(clk,data,sm_wei,sm_duan);

inputclk;

input[15:0] data;

output[3:0] sm_wei;

output[7:0] sm_duan;

//----------------------------------------------------------

//分频

integerclk_cnt;

regclk_400Hz;

always@(posedge clk)

if(clk_cnt==32'd100000)

beginclk_cnt <= 1'b0; clk_400Hz <= ~clk_400Hz;end

else

clk_cnt<= clk_cnt + 1'b1;

//----------------------------------------------------------

//位控制

reg[3:0]wei_ctrl=4'b1110;

always@(posedge clk_400Hz)

wei_ctrl<= {wei_ctrl[2:0],wei_ctrl[3]};

//段控制

reg[3:0]duan_ctrl;

always@(wei_ctrl)

case(wei_ctrl)

4'b1110:duan_ctrl=data[3:0];

4'b1101:duan_ctrl=data[7:4];

4'b1011:duan_ctrl=data[11:8];

4'b0111:duan_ctrl=data[15:12];

default:duan_ctrl=4'hf;

endcase

//----------------------------------------------------------

//解码模块

reg[7:0]duan;

always@(duan_ctrl)

case(duan_ctrl)

4'h0:duan=8'b1100_0000;//0

4'h1:duan=8'b1111_1001;//1

4'h2:duan=8'b1010_0100;//2

4'h3:duan=8'b1011_0000;//3

4'h4:duan=8'b1001_1001;//4

4'h5:duan=8'b1001_0010;//5

4'h6:duan=8'b1000_0010;//6

4'h7:duan=8'b1111_1000;//7

4'h8:duan=8'b1000_0000;//8

4'h9:duan=8'b1001_0000;//9

4'ha:duan=8'b1000_1000;//a

4'hb:duan=8'b1000_0011;//b

4'hc:duan=8'b1100_0110;//c

4'hd:duan=8'b1010_0001;//d

4'he:duan=8'b1000_0111;//e

4'hf:duan=8'b1000_1110;//f

// 4'hf:duan=8'b1111_1111;//不显示

default: duan = 8'b1100_0000;//0

endcase

//----------------------------------------------------------

assignsm_wei = wei_ctrl;

assignsm_duan = duan;

endmodule

//数码管显示程序

moduletest(clk,data,e,f,g,h,d);

inputclk;

inpute,f,g,h,d;

output[15:0]data;

//----------------------------------------------------------

//分频10Hz

regclk_10Hz;

integerclk_10Hz_cnt;

always@(posedge clk)

if(clk_10Hz_cnt==32'd2500000-1)

beginclk_10Hz_cnt <= 1'b0; clk_10Hz <= ~clk_10Hz;end

else

clk_10Hz_cnt<= clk_10Hz_cnt + 1'b1;

regclk_0_25Hz;

integerclk_0_25Hz_cnt;

always@(posedge clk)

if(clk_0_25Hz_cnt==32'd25000000-1)

beginclk_0_25Hz_cnt <= 1'b0; clk_0_25Hz <= ~clk_0_25Hz;end

else

clk_0_25Hz_cnt<= clk_0_25Hz_cnt + 1'b1;

//----------------------------------------------------------

regm,n;

reg[3:0] i;

reg[15:0]data = 16'b0;

always@(posedge clk_10Hz)

begin

if(e==1||f==1||g==1||h==1)

begin

m<= clk_0_25Hz;

n<= 1;

i[0]<= e;

i[1]<= f;

i[2]<= g;

i[3]<= h;

end

if(n&&(e==0&&f==0&&g==0&&h==0)&&(m^clk_0_25Hz))

begin

if(i[0]==1&&d==1)

data[15:8]<= data[15:8]+2;

if(i[1]==1&&d==1)

data[15:8]<= data[15:8]+1;

if(i[0]==1&&d==0)

data[15:8]<= data[15:8]-2;

if(i[1]==1&&d==0)

data[15:8]<= data[15:8]-1;

if(i[2]==1&&d==1)

data[7:0]<= data[7:0]+2;

if(i[3]==1&&d==1)

data[7:0]<= data[7:0]+1;

if(i[2]==1&&d==0)

data[7:0]<= data[7:0]-2;

if(i[3]==1&&d==0)

data[7:0]<= data[7:0]-1;

i<= 4'b0;

n<= 0;

end

endmodule

//顶层模块连接测试模块和数码管封装模块

//顶层模块

moduleshudian_2(clk,sm_wei,sm_duan,e,f,g,h,d);

inputclk;

inpute,f,g,h,d;

output[3:0]sm_wei;

output[7:0]sm_duan;

//----------------------------------------------------------

wire[15:0]data;

wire[3:0]sm_wei;

wire[7:0]sm_duan;

//----------------------------------------------------------

testU0 (.clk(clk),.data(data),.e(e),.f(f),.g(g),.h(h),.d(d));

shumaguanU1 (.clk(clk),.data(data),.sm_wei(sm_wei),.sm_duan(sm_duan));

endmodule

2.约束文件：

//ucf约束文件

NET "clk" LOC = B8;

NET "sm_duan[0]" LOC = L14;

NET "sm_duan[1]" LOC = H12;

NET "sm_duan[2]" LOC = N14;

NET "sm_duan[3]" LOC = N11;

NET "sm_duan[4]" LOC = P12;

NET "sm_duan[5]" LOC = L13;

NET "sm_duan[6]" LOC = M12;

NET "sm_duan[7]" LOC = N13;

NET "sm_wei[3]" LOC = K14;

NET "sm_wei[2]" LOC = M13;

NET "sm_wei[1]" LOC = J12;

NET "sm_wei[0]" LOC = F12;

NET"e"LOC=A7;

NET"f"LOC=M4;

NET"g"LOC=C11;

NET"h"LOC=G12;

NET"d"LOC=P11;

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