quartues编写的一个计数器，，modelsim仿真时的输出波形是直线。。付给初值后一直输出初值，clk显示正常
激励文件
library ieee; use ieee.std_logic_1164.all; entity clock_tb is end entity clock_tb; architecture behaviour of clock_tb is component clock port( clk: in std_logic; clr: in std_logic; seg: out std_logic_vector(7 downto 0); dig: buffer std_logic_vector(2 downto 0) ); end component; signal clk:std_logic; signal clr:std_logic; signal seg:std_logic_vector(7 downto 0):="01000000"; signal dig:std_logic_vector(2 downto 0):="000";
begin u1: clock port map( clk=>clk, clr=>clr, seg=>seg, dig=>dig); process begin wait for 10 ns; clk<='1'; wait for 10 ns; clk<='0'; end process; process begin wait for 0 ns; clr <= '0'; --复位开始 wait for 200.1 ns; clr <= '1'; --复位完成 wait; --持续等待 end process; end architecture behaviour;
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