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module clk_div1Hz(clk_50M,clk_1Hz);
input clk_50M;
output clk_1Hz;
reg clk_1Hz;
reg [25:0]count;
parameter cnt = 25;
always@(posedge clk_50M)
begin
count <= count + 1'b1;
if(count == cnt - 1)
begin
count <= 0;
clk_1Hz <= !clk_1Hz;
end
end
endmodule
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