LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY Vhdl1 IS
PORT (CP,R,EN:IN STD_LOGIC;
CO:OUT BIT;
Y:OUT INTEGER RANGE 0 TO 10;
LED : out std_logic_vector(6 downto 0));
END Vhdl1;
architecture RT of Vhdl1 is
signal Q:INTEGER RANGE 0 TO 10;
BEGIN
PROCESS(CP,R,EN)
BEGIN
IF R='1' THEN Q<=0;
ELSIF(EN = '1')THEN
IF(CP'EVENT AND CP='1')THEN
IF Q=9 THEN
CO<='1';
Q<=0;
ELSE
Q<=Q+1;
CO<='0';
END IF;
END if;
END IF;
Y<=Q;
END PROCESS;
with Q select
LED<="1000000" when 0,
"1111001" when 1,
"0100100" when 2,
"0110000" when 3,
"0011001" when 4,
"0010010" when 5,
"0000010" when 6,
"1111000" when 7,
"0000000" when 8,
"0010000" when 9,
"1111111" when others;
END RT;
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