EDA 汽车尾灯控制器设计VHDL源码

EDA作业


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汽车尾灯控制器设计.rar (363.1 KB, 下载次数: 64)

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1. Library ieee;
   
2. Use ieee.std_logic_1164.all;
   
3. Use ieee.std_logic_unsigned.all;
   
4. Entity tp is
   
5. Port(clk:in std_logic;
   
6.         Left:in std_logic;
   
7.         Right:in std_logic;
   
8.         Brake:in std_logic;
   
9.         Night:in std_logic;
   
10.         Ld1,Ld2,Ld3:out std_logic;
    
11.         Rd1,Rd2,Rd3:out std_logic);
    
12. End;
    
13. Architecture bh of tp is
    
14. Component sz is
    
15.         Port(clk:in std_logic;
    
16.         Cp:out std_logic);
    
17. End component;
    
18. Component ctrl is
    
19.         Port(left,right,brake,night:in std_logic;
    
20.         Lp,rp,lr,brake_led,night_led:out std_logic);
    
21. End component;
    
22. Component lc is
    
23.         Port(clk,lp,lr,brake,night:in std_logic;
    
24.         Ledl,ledb,ledn:out std_logic);
    
25. End component;
    
26. Component rc is
    
27.         Port(clk,rp,lr,brake,night:in std_logic;
    
28.         Ledr,ledb,ledn:out std_logic);
    
29. End component;
    
30. Signal tmp0,tmp1,tmp2,tmp3,tmp4:std_logic;
    
31. Signal err0,err1,err2,err3,err4,err5:std_logic;
    
32. signal bm:std_logic;
    
33. Begin
    
34. U1:sz port map(clk,bm);
    
35. U2:ctrl port map(left,right,brake,night,tmp0,tmp1,tmp2,tmp3,tmp4);
    
36. U3:lc port map(clk,tmp0,tmp2,tmp3,tmp4,err0,err1,err2);
    
37. U4:rc port map(clk,tmp1,tmp2,tmp3,tmp4,err3,err4,err5);
    
38. Ld1<=err0 and bm;
    
39. Ld2<=err1;
    
40. Ld3<=err2;
    
41. Rd1<=err3 and bm;
    
42. Rd2<=err4;
    
43. Rd3<=err5;
    
44. End;

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