利用元件例化VHDL语言编写的六位数字频率计源码

Cnt10/10进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk,clr,en:in std_logic;
                carry_out:out std_logic;
      cq:out std_logic_vector(3 downto 0));
    end cnt10;
architecture bhv of cnt10 is
signal cnt:std_logic_vector(3 downto 0);
begin
    cq<=cnt;
    process(clr,en,clk)
begin
        if clr='1' then
        cnt <= "0000";
        elsif clk'event and clk='1' then
                if (en='1') then
                        if cnt="1001" then cnt<="0000";
                                carry_out<='1';
                        else cnt<=cnt+1;
                                carry_out<='0';
                        end if;
                end if;
        end if;
end process;
end bhv;

Cnt10x6 /六合一十进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10x6 is
port(fx,clr,en:in std_logic;
      q:out std_logic_vector(23 downto 0));
    end cnt10x6;
architecture a of cnt10x6 is
component cnt10
port(clk,clr,en:in std_logic;
                carry_out:out std_logic;
      cq:out std_logic_vector(3 downto 0));
      end component;
      signal c:std_logic_vector(5 downto 0);
      begin
u1:cnt10 port map(clk=>fx,clr=>clr,en=>en,cq=>q(3 downto 0),carry_out=>c(0));
u2:cnt10 port map(clk=>c(0),clr=>clr,en=>en,cq=>q(7 downto 4),carry_out=>c(1));
u3:cnt10 port map(clk=>c(1),clr=>clr,en=>en,cq=>q(11 downto 8),carry_out=>c(2));
u4:cnt10 port map(clk=>c(2),clr=>clr,en=>en,cq=>q(15 downto 12),carry_out=>c(3));
u5:cnt10 port map(clk=>c(3),clr=>clr,en=>en,cq=>q(19 downto 16),carry_out=>c(4));
u6:cnt10 port map(clk=>c(4),clr=>clr,en=>en,cq=>q(23 downto 20),carry_out=>c(5));
end a;

Reg24 锁存器
library ieee;
use ieee.std_logic_1164.all;
entity reg24 is
port(load:in std_logic;
din:in std_logic_vector(23 downto 0);
dout:out std_logic_vector(23 downto 0));
end;
architecture rtl of reg24 is
begin
        process(load)
        begin
        if (load'event and load='1') then dout<=din;
        end if;
        end process;
end rtl;

Fp 分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp is
port(clkin:in std_logic;
                clkout:out std_logic);
end ;
architecture rtl of fp is
signal tmp:integer range 0 to 500;
begin
process(clkin)
begin
if clkin'event and clkin='1' then
        if tmp=499 then
                tmp<=0;
        else tmp<=tmp+1;
        end if;
end if;
if tmp=249 then
        clkout<='1';
        else clkout<='0';
end if;
end process;
end rtl;

Ctrl 频率控制器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl is
port(clk:in std_logic;
                en,load,clr:out std_logic);
end ;
architecture rtl of ctrl is
signal tmp:std_logic;
begin
process(clk)
begin
    if clk'event and clk='1' then
        tmp<=not tmp;
        end if;

        en<=tmp;
        load<=not tmp;

if clk='0'and tmp='0' then
clr<='1';
else
clr<='0';
end if;
end process;
end rtl;

Disp 动态显示
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity disp is
port(din:in std_logic_vector(23 downto 0);clk:in std_logic;
        wk:out std_logic_vector(5 downto 0);
        dm:out std_logic_vector(6 downto 0));
end;
architecture str of disp is
signal tmp:std_logic_vector(2 downto 0);
signal do:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
tmp<=tmp+1;
end if;
end process;
process(tmp)
begin
      case tmp is
      when "000"=>wk<="111110";do<=din(3 downto 0);
      when "001"=>wk<="111101";do<=din(7 downto 4);
      when "010"=>wk<="111011";do<=din(11 downto 8);
      when "011"=>wk<="110111";do<=din(15 downto 12);
      when "100"=>wk<="101111";do<=din(19 downto 16);
      when "101"=>wk<="011111";do<=din(23 downto 20);
      when others=>wk<="111111";do<="0000";
      end case;
      end process;

process(do)
begin
case do is
when"0000"=>dm<="0111111";
when"0001"=>dm<="0000110";
when"0010"=>dm<="1011011";
when"0011"=>dm<="1001111";
when"0100"=>dm<="1100110";
when"0101"=>dm<="1101001";
when"0110"=>dm<="1111101";
when"0111"=>dm<="0000111";
when"1000"=>dm<="1111111";
when"1001"=>dm<="1101111";
when others=>dm<="0000000";
end case;
end process;
end str;

Plj 打包
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity plj is
port(fx,clk:in std_logic;
        wk:out std_logic_vector(5 downto 0);
        dm:out std_logic_vector(6 downto 0));
    end plj;
architecture a of plj is
component cnt10x6
port(fx,clr,en:in std_logic;
      q:out std_logic_vector(23 downto 0));
      end component;
component reg24
port(load:in std_logic;
din:in std_logic_vector(23 downto 0);
dout:out std_logic_vector(23 downto 0));
end component;

component disp
port(din:in std_logic_vector(23 downto 0);clk:in std_logic;
        wk:out std_logic_vector(5 downto 0);
        dm:out std_logic_vector(6 downto 0));
end component;

component fp
port(clkin:in std_logic;
                clkout:out std_logic);
end component;

component ctrl
port(clk:in std_logic;
                en,load,clr:out std_logic);
end component;
signal c,en1,load1,clr1:std_logic;
signal din1,dout1:std_logic_vector(23 downto 0);
begin
u1:fp port map(clk,c);
u2:ctrl port map(c,en1,load1,clr1);
u3:cnt10x6 port map(fx,clr1,en1,din1);
u4:reg24 port map(load1,din1,dout1);
u5:disp port map(dout1,clk,wk,dm);
end a;