VHDL编程60s时钟及显示程序

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity dianzibiao is
Port(clk,key:in std_logic;
     ww:out std_logic_vector(1 downto 0);
     qqq:out std_logic_vector(3 downto 0);
   Q:out std_logic_vector(6 downto 0));
end;
Architecture dzb of dianzibiao is
signal q1,q2,disp:std_logic_vector(3 downto 0);
signal tt:std_logic_vector(7 downto 0);
signal d1,d2,d3,d4,cp,c1,c2:std_logic;
signal t:std_logic_vector(25 downto 0);
begin
    process(clk)
     begin
      if clk'event and clk='1' then t<=t+1;tt<=tt+1;
        if t=19999999 then
         t<="00000000000000000000000000";c1<='1';
        else c1<='0';
        end if;
     end if;
    end process;
----------------------------
process(c1)
begin
if c1'event and c1='1' then q1<=q1+1;
   if q1=9 then q1<="0000";q2<=q2+1;  
   end if;
   if q2=5 and q1=9 then q2<="0000";
   end if;
  end if;
end process;
  ------------------------------
process(q1,q2)
   begin
   if tt<128 then disp<=q1;ww<="01";       --位显示1显示，0不显示
   else disp<=q2;ww<="10";
   end if;
end process;
----------------------------  
process(disp)
begin  
   case disp is
      when "0000"=>Q<="0000001";     --段码显示开发板共阳极，所以0显示，1不显示。
      when "0001"=>Q<="1001111" ;
      when "0010"=>Q<="0010010" ;
      when "0011"=>Q<="0000110" ;
      when "0100"=>Q<="1001100" ;
      when "0101"=>Q<="0100100" ;
      when "0110"=>Q<="0100000" ;
      when "0111"=>Q<="0001111" ;
      when "1000"=>Q<="0000000" ;
      when "1001"=>Q<="0000100" ;
      when others=>null;
      end case;
     end process;
end;

表示看不明白呀