基于FPGA的多功能电子钟设计与实现

ID:357868 · 发表于 2018-6-24 16:46

功能要求与技术指标

1.电子时钟。要求用24时制显示。分屏显示“时、分”和“分、秒”，即4个数码管不能同时显示“时、分、秒”，但可以只显示“时、分”，或只显示“分、秒”，通过按键来切换这两种显示方式。用数码管的小数点“.”代替时、分、秒的分隔符“：”。可设置时间。设置时间时，当前设置的“时”/“分”，相应的数码管应闪烁。

2.秒表（计时器）。秒表精度为0.01秒，计时范围0~99.99秒，用4个数码管显示，两个显示秒，两个显示百分秒，有暂停/继续、重置（清零）按钮。

3.定时器。可以实现0~9999秒定时。设置一定时值，当计时到达设定值时输出LED闪烁。有设置、暂停/继续、清零定时按钮。

1.管脚分配
#Scnu_pins.tcl
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assignment PIN_17 -to clk
set_location_assignment PIN_71 -to led
set_location_assignment PIN_65 -to seg7com\[0\]
set_location_assignment PIN_67 -to seg7com\[1\]
set_location_assignment PIN_69 -to seg7com\[2\]
set_location_assignment PIN_70 -to seg7com\[3\]
set_location_assignment PIN_53 -to seg7data\[0\]
set_location_assignment PIN_55 -to seg7data\[1\]
set_location_assignment PIN_57 -to seg7data\[2\]
set_location_assignment PIN_58 -to seg7data\[3\]
set_location_assignment PIN_59 -to seg7data\[4\]
set_location_assignment PIN_60 -to seg7data\[5\]
set_location_assignment PIN_63 -to seg7data\[6\]
set_location_assignment PIN_64 -to seg7data\[7\]
set_location_assignment PIN_88 -to key1
set_location_assignment PIN_89 -to key2
set_location_assignment PIN_90 -to key3
set_location_assignment PIN_91 -to key4
set_location_assignment PIN_72 -to key5
--set_location_assignment PIN_64 -to seg7dp
2.顶层top.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity top is
port(key1,key2,key3,key4,key5,clk:in std_logic;
led:out std_logic;
seg7data:out std_logic_vector(7 downto 0);
seg7com:out std_logic_vector(3 downto 0));
end entity top;
architecture example of top is
--调用声明
component fandou is
port(clk,fin:in std_logic;
fout:out std_logic);
end component fandou;
component div_hz is
port(clk:in std_logic;
clk_out:out std_logic);
end component div_hz;
component div_10hz is
port(clk:in std_logic;
clk_out:out std_logic);
end component div_10hz;
component div_100hz is
port(clk:in std_logic;
clk_out:out std_logic);
end component div_100hz;
component div_khz is
port(clk:in std_logic;
clk_out:out std_logic);
end component div_khz;
component clock is
port(clk,set,plus,clr:in std_logic;
set_data1,set_data2,set_data3,set_data4:in std_logic_vector(3 downto 0);
clock_data1,clock_data2,clock_data3,clock_data4,clock_data5,clock_data6:out std_logic_vector(3 downto 0));
end component clock;
component watch is
port(clk,plus,clr:in std_logic;
watch_data1,watch_data2,watch_data3,watch_data4:out std_logic_vector(3 downto 0));
end component watch;
component timer is
port(clk,mov,plus,clr:in std_logic;
set_data1,set_data2,set_data3,set_data4:in std_logic_vector(3 downto 0);
timer_data1,timer_data2,timer_data3,timer_data4:out std_logic_vector(3 downto 0));
end component timer;
component setting is
port(set,mov,plus:in std_logic;
set_data1,set_data2,set_data3,set_data4:out std_logic_vector(3 downto 0));
end component setting;
component shining is
port(clk,set,mov:in std_logic;
com:in std_logic_vector(3 downto 0);
seg7com:out std_logic_vector(3 downto 0));
end component shining;
component displayer is
port(clk:in std_logic;
data1,data2,data3,data4:in std_logic_vector(3 downto 0);
seg7com:out std_logic_vector(3 downto 0);
seg7data:out std_logic_vector(7 downto 0));
end component displayer;
--定义信号量
signal setn,mov,plus,clr,moden:std_logic;
signal clk_hz,clk_10hz,clk_100hz,clk_khz:std_logic;
signal set:std_logic;
signal mode:std_logic_vector(3 downto 0):="0000";
signal data1,data2,data3,data4:std_logic_vector(3 downto 0):="0000";
signal set_data1,set_data2,set_data3,set_data4:std_logic_vector(3 downto 0):="0000";
signal clock_data1,clock_data2,clock_data3,clock_data4,clock_data5,clock_data6:std_logic_vector(3 downto 0);
signal watch_data1,watch_data2,watch_data3,watch_data4:std_logic_vector(3 downto 0);
signal timer_data1,timer_data2,timer_data3,timer_data4:std_logic_vector(3 downto 0);
signal com:std_logic_vector(3 downto 0);
begin
process(moden)is—mod按键置数
begin
if(moden'event and moden='1')then
if(mode="0011")then
mode<="0000";
else
mode<=mode+'1';
end if;
end if;
end process;
process(setn)is—set按键
begin
if(setn'event and setn='1')then
set<=not set;
end if;
end process;
process(set,mode)is—选通不同模块的data进行显示
begin
if(set='1')then
data1<=set_data1;
data2<=set_data2;
data3<=set_data3;
data4<=set_data4;
elsif(set='0')then
if(mode="0000")then
data1<=clock_data3;
data2<=clock_data4;
data3<=clock_data5;
data4<=clock_data6;
elsif(mode="0001")then
data1<=clock_data1;
data2<=clock_data2;
data3<=clock_data3;
data4<=clock_data4;
elsif(mode="0010")then
data1<=watch_data1;
data2<=watch_data2;
data3<=watch_data3;
data4<=watch_data4;
elsif(mode="0011")then
data1<=timer_data1;
data2<=timer_data2;
data3<=timer_data3;
data4<=timer_data4;
end if;
end if;
end process;
--按键1消抖
fandou1:fandou port map(
clk=>clk,
fin=>key1,
fout=>setn);
--按键2消抖
fandou2:fandou port map(
clk=>clk,
fin=>key2,
fout=>mov);
--按键3消抖
fandou3:fandou port map(
clk=>clk,
fin=>key3,
fout=>plus);
--按键4消抖
fandou4:fandou port map(
clk=>clk,
fin=>key4,
fout=>clr);
--按键5消抖
fandou5:fandou port map(
clk=>clk,
fin=>key5,
fout=>moden);
--秒分频
name_div_hz:div_hz port map(
clk=>clk,
clk_out=>clk_hz);
--100毫秒分频
name_div_10hz:div_10hz port map(
clk=>clk,
clk_out=>clk_10hz);
--10毫秒分频
name_div_100hz:div_100hz port map(
clk=>clk,
clk_out=>clk_100hz);
--毫秒分频
name_div_khz:div_khz port map(
clk=>clk,
clk_out=>clk_khz);
--时钟模块
name_clock:clock port map(
clk=>clk_hz,
set=>set,
plus=>not plus,
clr=>not clr,
set_data1=>set_data1,
set_data2=>set_data2,
set_data3=>set_data3,
set_data4=>set_data4,
clock_data1=>clock_data1,
clock_data2=>clock_data2,
clock_data3=>clock_data3,
clock_data4=>clock_data4,
clock_data5=>clock_data5,
clock_data6=>clock_data6);
--秒表模块
name_watch:watch port map(
clk=>clk_100hz,
plus=>not plus,
clr=>not clr,
watch_data1=>watch_data1,
watch_data2=>watch_data2,
watch_data3=>watch_data3,
watch_data4=>watch_data4);
--定时器模块
name_timer:timer port map(
clk=>clk_hz,
mov=>mov,
plus=>not plus,
clr=>not clr,
set_data1=>set_data1,
set_data2=>set_data2,
set_data3=>set_data3,
set_data4=>set_data4,
timer_data1=>timer_data1,
timer_data2=>timer_data2,
timer_data3=>timer_data3,
timer_data4=>timer_data4);
--置数模块
name_set:setting port map(
set=>not set,
mov=>not mov,
plus=>not plus,
set_data1=>set_data1,
set_data2=>set_data2,
set_data3=>set_data3,
set_data4=>set_data4);
--闪烁模块
name_shine:shining port map(
clk=>clk_10hz,
set=>not set,
mov=>not mov,
com=>com,
seg7com=>seg7com);
--显示模块
display:displayer port map(
clk=>clk_khz,
data1=>data1,
data2=>data2,
data3=>data3,
data4=>data4,
seg7com=>com,
seg7data=>seg7data);
end architecture example;
3.消抖fandou.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fandou IS
port(clk,fin:in std_logic;
fout:out std_logic);
end entity fandou;
architecture example of fandou is
begin
process(fin,clk)
variable count:integer range 0 to 50000;
begin
if(fin='0')then
if(clk'event and clk='1')then
if(count<50000)then
count:=count+1;
else
count:=count;
end if;
if(count<50000)then
fout<='1';
else
fout<='0';
end if;
end if;
else
count:=0;
fout<='1';
end if;
end process;
end architecture example;
4.100毫秒分频div_10hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_10hz is
port(clk:in std_logic;
clk_out:out std_logic);
end entity div_10hz;
architecture example of div_10hz is
begin
process(clk)is
variable counter:integer range 0 to 5000000;
begin
if(clk'event and clk='1')then
if (counter=5000000)then
counter:=0;
clk_out<='1';
else
counter:=counter+1;
clk_out<='0';
end if;
end if;
end process;
end architecture example;
5.10毫秒分频div_100hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_100hz is
port(clk:in std_logic;
clk_out:out std_logic);
end entity div_100hz;
architecture example of div_100hz is
begin
process(clk)is
variable counter:integer range 0 to 500000;
begin
if(clk'event and clk='1')then
if (counter=500000)then
counter:=0;
clk_out<='1';
else
counter:=counter+1;
clk_out<='0';
end if;
end if;
end process;
end architecture example;
5.秒分频div_hz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_hz is
port(clk:in std_logic;
clk_out:out std_logic);
end entity div_hz;
architecture example of div_hz is
begin
process(clk)is
variable counter:integer range 0 to 50000000;
begin
if(clk'event and clk='1')then
if (counter=50000000)then
counter:=0;
clk_out<='1';
else
counter:=counter+1;
clk_out<='0';
end if;
end if;
end process;
end architecture example;
6.毫秒分频div_khz.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div_khz is
port(clk:in std_logic;
clk_out:out std_logic);
end entity div_khz;
architecture example of div_khz is
begin
process(clk)is
variable counter:integer range 0 to 50000;
begin
if(clk'event and clk='1')then
if (counter=50000)then
counter:=0;
clk_out<='1';
else
counter:=counter+1;
clk_out<='0';
end if;
end if;
end process;
end architecture example;
7.时钟clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk,set,plus,clr:in std_logic;
set_data1,set_data2,set_data3,set_data4:in std_logic_vector(3 downto 0);
clock_data1,clock_data2,clock_data3,clock_data4,clock_data5,clock_data6:out std_logic_vector(3 downto 0));
end entity clock;
architecture example of clock is
component count60 is
port(clk,clr,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end component count60;
component count24 is
port(clk,clr,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end component count24;
--定义信号量
signal data1,data2,data3,data4,data5,data6:std_logic_vector(3 downto 0):="0000";
signal co1,co2,co3:std_logic;
begin
--输出赋值
clock_data1<=data1;
clock_data2<=data2;
clock_data3<=data3;
clock_data4<=data4;
clock_data5<=data5;
clock_data6<=data6;
--秒计数
count1:count60 port map(
clk=>clk,
clr=>clr,
wr=>'0',
cin=>'1',
co=>co1,
data_in1=>"0000",
data_in2=>"0000",
data_out1=>data1,
data_out2=>data2);
--分计数
count2:count60 port map(
clk=>clk,
clr=>clr,
wr=>plus,
cin=>co1,
co=>co2,
data_in1=>set_data1,
data_in2=>set_data2,
data_out1=>data3,
data_out2=>data4);
--时计数
count3:count24 port map(
clk=>clk,
clr=>clr,
wr=>plus,
cin=>co2,
co=>co3,
data_in1=>set_data3,
data_in2=>set_data4,
data_out1=>data5,
data_out2=>data6);
end architecture example;
8.秒表watch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity watch is
port(clk,plus,clr:in std_logic;
watch_data1,watch_data2,watch_data3,watch_data4:out std_logic_vector(3 downto 0));
end entity watch;
architecture example of watch is
--component申明
component count100 is
port(clk,clr,en,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end component count100;
--定义信号量
signal data1,data2,data3,data4:std_logic_vector(3 downto 0):="0000";
signal co0,co1,co2,co3,co4:std_logic;
signal plusn:std_logic:='1';
begin
--输出赋值
watch_data1<=data1;
watch_data2<=data2;
watch_data3<=data3;
watch_data4<=data4;
--判断plus按下
process(plus)is
begin
if(plus'event and plus='1')then
plusn<=not plusn;
end if;
end process;
--个位、十位计数
count1:count100 port map(
clk=>clk,
clr=>clr,
en=>plusn,
wr=>'0',
cin=>'1',
co=>co1,
data_in1=>"0000",
data_in2=>"0000",
data_out1=>data1,
data_out2=>data2);
--百位、千位计数
count2:count100 port map(
clk=>clk,
clr=>clr,
en=>plusn,
wr=>'0',
cin=>co1,
co=>co2,
data_in1=>"0000",
data_in2=>"0000",
data_out1=>data3,
data_out2=>data4);
end architecture example;
9.定时器timer.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timer is
port(clk,mov,plus,clr:in std_logic;
set_data1,set_data2,set_data3,set_data4:in std_logic_vector(3 downto 0);
timer_data1,timer_data2,timer_data3,timer_data4:out std_logic_vector(3 downto 0));
end entity timer;
architecture example of timer is
--component申明
component dcount100 is
port(clk,clr,en,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end component dcount100;
--定义信号量
signal data1,data2,data3,data4:std_logic_vector(3 downto 0):="0000";
signal co1,co2,co3,co4:std_logic;
signal plusn,movn:std_logic:='1';
signal ant,antn:std_logic;
begin
--输出赋值
timer_data1<=data1;
timer_data2<=data2;
timer_data3<=data3;
timer_data4<=data4;
--判断按键mov按下
process(mov)is
begin
if(mov'event and mov='1')then
movn<=not movn;
end if;
end process;
--判断倒计数为0暂停
process(clk)is
begin
if(data1="0000" and data2="0000" and data3="0000" and data4="0000")then
antn<='1';
end if;
end process;
process(antn)is
begin
if(antn'event and antn='1')then
ant<=not ant;
end if;
end process;
--个位、十位倒计数
count1:dcount100 port map(
clk=>clk,
clr=>clr,
en=>movn or ant,
wr=>plus,
cin=>'1',
co=>co1,
data_in1=>set_data1,
data_in2=>set_data2,
data_out1=>data1,
data_out2=>data2);
--百位、千位倒计数
count2:dcount100 port map(
clk=>clk,
clr=>clr,
en=>movn or ant,
wr=>plus,
cin=>co1,
co=>co2,
data_in1=>set_data3,
data_in2=>set_data4,
data_out1=>data3,
data_out2=>data4);
end architecture example;
10.100进制计数器count100.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count100 is
port(clk,clr,en,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end entity count100;
architecture example of count100 is
--信号量定义
signal data1:std_logic_vector(3 downto 0);
signal data2:std_logic_vector(3 downto 0);
begin
data_out1<=data1;
data_out2<=data2;
--个位计数
process(clk,wr)is
begin
if(clr='1')then
data1<="0000";
elsif(wr='1')then
data1<=data_in1;
elsif(clk'event and clk='1')then
if(en='0')then
if(cin='1')then
if(data1=9)then
data1<="0000";
else
data1<=data1+1;
end if;
end if;
end if;
end if;
end process;
--十位计数
process(clk,wr)is
begin
if(clr='1')then
data2<="0000";
elsif(wr='1')then
data2<=data_in2;
elsif(clk'event and clk='1')then
if(en='0')then
if(cin='1' and data1=9)then
if(data2=9)then
data2<="0000";
else
data2<=data2+1;
end if;
end if;
end if;
end if;
end process;
--进位判断
process(data1,data2,cin)is
begin
if(cin='1'and data1=9 and data2=9)then
co<='1';
else
co<='0';
end if;
end process;
end architecture example;
11.100进制倒计数器dcount100.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dcount100 is
port(clk,clr,en,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end entity dcount100;
architecture example of dcount100 is
--信号量定义
signal data1:std_logic_vector(3 downto 0);
signal data2:std_logic_vector(3 downto 0);
begin
data_out1<=data1;
data_out2<=data2;
--个位计数
process(clk,wr,en)is
begin
if(clr='1')then
data1<="0000";
elsif(wr='1')then
data1<=data_in1;
elsif(clk'event and clk='1')then
if(en='0')then
if(cin='1')then
if(data1=0)then
data1<="1001";
else
data1<=data1-1;
end if;
end if;
end if;
end if;
end process;
--十位计数
process(clk,wr)is
begin
if(clr='1')then
data2<="0000";
elsif(wr='1')then
data2<=data_in2;
elsif(clk'event and clk='1')then
if(en='0')then
if(cin='1' and data1=0)then
if(data2=0)then
data2<="1001";
else
data2<=data2-1;
end if;
end if;
end if;
end if;
end process;
--进位判断
process(data1,data2,cin)is
begin
if(cin='1'and data1=0 and data2=0)then
co<='1';
else
co<='0';
end if;
end process;
end architecture example;
12.60进制计数器count60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
port(clk,clr,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end entity count60;
architecture example of count60 is
signal data1:std_logic_vector(3 downto 0);
signal data2:std_logic_vector(3 downto 0);
begin
data_out1<=data1;
data_out2<=data2;
process(clk,wr)is
begin
if(clr='1')then
data1<="0000";
elsif(wr='1')then
data1<=data_in1;
elsif(clk'event and clk='1')then
if(cin='1')then
if(data1=9)then
data1<="0000";
else
data1<=data1+1;
end if;
end if;
end if;
end process;
process(clk,wr)is
begin
if(clr='1')then
data2<="0000";
elsif(wr='1')then
data2<=data_in2;
elsif(clk'event and clk='1')then
if(cin='1' and data1=9)then
if(data2=5)then
data2<="0000";
else
data2<=data2+1;
end if;
end if;
end if;
end process;
process(data1,data2,cin)is
begin
if(cin='1'and data1=9 and data2=5)then
co<='1';
else
co<='0';
end if;
end process;
end architecture example;
13.24进制计数器count24.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count24 is
port(clk,clr,wr,cin:in std_logic;
co:out std_logic;
data_in1:in std_logic_vector(3 downto 0);
data_in2:in std_logic_vector(3 downto 0);
data_out1:out std_logic_vector(3 downto 0);
data_out2:out std_logic_vector(3 downto 0));
end entity count24;
architecture example of count24 is
signal data1:std_logic_vector(3 downto 0);
signal data2:std_logic_vector(3 downto 0);
begin
data_out1<=data1;
data_out2<=data2;
process(clk,wr)is
begin
if(clr='1')then
data1<="0000";
elsif(wr='1')then
data1<=data_in1;
elsif(clk'event and clk='1')then
if(cin='1')then
if(data1=9)then
data1<="0000";
else
data1<=data1+1;
end if;
end if;
if(cin='1'and data1=3 and data2=2)then
data1<="0000";
end if;
end if;
end process;
process(clk,wr,cin)is
begin
if(clr='1')then
data2<="0000";
elsif(wr='1')then
data2<=data_in2;
elsif(clk'event and clk='1')then
if(cin='1' and data1=9)then
if(data2=2)then
data2<="0000";
else
data2<=data2+1;
end if;
end if;
if(cin='1'and data1=3 and data2=2)then
data2<="0000";
end if;
end if;
end process;
process(data1,data2,cin)is
begin
if(cin='1'and data1=3 and data2=2)then
co<='1';
else
co<='0';
end if;
end process;
end architecture example;
14.置数模块 setting.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity setting is
port(set,mov,plus:in std_logic;
set_data1,set_data2,set_data3,set_data4:out std_logic_vector(3 downto 0));
end entity setting;
architecture example of setting is
signal data1,data2,data3,data4:std_logic_vector(3 downto 0):="0000";
signal count:std_logic_vector(3 downto 0):="0000";
begin
set_data1<=data1;
set_data2<=data2;
set_data3<=data3;
set_data4<=data4;
--选通一路输出加1
process(set,plus,count)is
begin
if(set='0')then
if(plus'event and plus='1')then
case count is
when "0000"=>data1<=data1+'1';
when "0001"=>data2<=data2+'1';
when "0010"=>data3<=data3+'1';
when "0011"=>data4<=data4+'1';
when others=>NULL;
end case;
end if;
end if;
end process;
process(mov,count)is
begin
if(mov'event and mov='1')then
if(count="0011")then
count<="0000";
else
count<=count+'1';
end if;
end if;
end process;
end architecture example;
15.闪烁模块 shining.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shining is
port(clk,set,mov:in std_logic;--秒脉冲，设置键，移位键
com:in std_logic_vector(3 downto 0);
seg7com:out std_logic_vector(3 downto 0));
end entity shining;
architecture example of shining is
signal count:std_logic_vector(3 downto 0):="0000";
signal com2:std_logic_vector(3 downto 0);
signal squ:std_logic;
begin
process(mov)is
variable dot: integer range 0 to 3;
begin
if(mov'event and mov='1')then--按下移位键
if(dot=3)then
dot:=0;
else
dot:=dot+1;
end if;
case dot is
when 0=>count<="1000";
when 1=>count<="0100";
when 2=>count<="0010";
when 3=>count<="0001";
when others=>null;
end case;
end if;
end process;
process(clk)is
begin
if(clk'event and clk='1')then
squ<=not squ;
end if;
end process;
--按下set闪烁
process(set,com,squ)is
begin
if(set='1')then
com2<="0000";
elsif(set='0')then
com2<=count;
end if;
--或运算
if(squ='1')then
seg7com<=com or com2;
else
seg7com<=com;
end if;
end process;
end architecture example;
16.显示模块 displayer.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity displayer is
port(clk:in std_logic;
data1,data2,data3,data4:in std_logic_vector(3 downto 0);
seg7com:out std_logic_vector(3 downto 0);
seg7data:out std_logic_vector(7 downto 0));
end entity displayer;
architecture example of displayer is
component seg7led is
port(bcd_in:in std_logic_vector(3 downto 0);
dot:in std_logic;
data_out:out std_logic_vector(7 downto 0));
end component seg7led;
signal data:std_logic_vector(3 downto 0);
signal dot,setn:std_logic;
begin
led:seg7led port map(
bcd_in=>data,
dot=>dot,
data_out=>seg7data);
--选通四路输出扫频
process(clk)is
variable count: integer range 0 to 3;
begin
if(clk'event and clk='0')then
if(count=3)then
count:=0;
else
count:=count+1;
end if;
case count is
when 0=>seg7com<="0111";data<=data1;dot<='1';
when 1=>seg7com<="1011";data<=data2;dot<='1';
when 2=>seg7com<="1101";data<=data3;dot<='0';
when 3=>seg7com<="1110";data<=data4;dot<='1';
when others=>null;
end case;
end if;
end process;
end architecture example;
17.4-7译码器 seg7led.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY seg7led IS
PORT(bcd_in:IN STD_LOGIC_VECTOR(3 downto 0);
dot:in std_logic;
data_out:OUT STD_LOGIC_VECTOR(7 downto 0));
END seg7led;
ARCHITECTURE example OF seg7led IS
signal data:std_LOGIC_VECTOR(6 downto 0);
BEGIN
data_out(0)<=data(0);
data_out(1)<=data(1);
data_out(2)<=data(2);
data_out(3)<=data(3);
data_out(4)<=data(4);
data_out(5)<=data(5);
data_out(6)<=data(6);
data_out(7)<=dot;
process(bcd_in)
begin
case bcd_in is
when "0000" => data <= "1000000";
when "0001" => data <= "1111001";
when "0010" => data <= "0100100";
when "0011" => data <= "0110000";
when "0100" => data <= "0011001";
when "0101" => data <= "0010010";
when "0110" => data <= "0000010";
when "0111" => data <= "1111000";
when "1000" => data <= "0000000";
when "1001" => data <= "0010000";
when others => NULL;
end case;
end process;
END example;

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