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module F50M_1(reset,clk_in,f1hz_out); input reset,clk_in; output f1hz_out; reg f1hz_out; reg[31:0]count;
always@(posedge clk_in or negedge reset) if(!reset) begin f1hz_out<=0; count<=0;
end else begin if(count==24999999)//0.5s begin count<=0; f1hz_out<=~f1hz_out; end else count<=count+1; end endmodule /////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// //顶层模块 module SEG(k1,k2,k3,stop,clr,clk_in,sec1,sec2,min1,min2,hou1,hou2); input stop,clr,clk_in,k1,k2,k3; output sec1,sec2,min1,min2,hou1,hou2; reg [7:0]sec1,sec2,min1,min2,hou1,hou2;
reg[3:0] second1; reg[3:0]minute1; reg[3:0]hour1; reg[2:0]second2; reg[2:0]minute2; reg[1:0]hour2;
wire f1hz_out; F50M_1(stop,clk_in,f1hz_out);//调用一个元件，上面的分频器，例化语句
always@(posedge f1hz_out or negedge clr ) begin if(!clr) begin second1<=0 ; second2<=0 ; minute1<=0 ; minute2<=0 ; hour1<=0 ; hour2<=0 ; // sec<=8'hc0; //0 end else if(!k1) begin if(second1==9)//0.5s begin second1<=0 ; if(second2==5) begin second2<=0 ; end else begin
second2<=second2+1; end
end else begin second1<=second1+1; end
end else if(!k2) begin if(minute1==9)//0.5s begin minute1<=0 ; if(minute2==5) begin minute2<=0 ; end else begin
minute2<=minute2+1; end
end else begin minute1<=minute1+1; end
end else if(!k3) begin if(hour1==9) begin hour1<=0; hour2<=hour2+1; end else begin hour1<=hour1+1; end if((hour2==2)&&(hour1==3)) begin hour1<=0; hour2<=0; end
end
else begin if(second1==9)//0.5s begin second1<=0 ; if(second2==5) begin second2<=0 ; if(minute1==9) begin minute1<=0;
if(minute2==5) begin minute2<=0; if(hour1==9) begin hour1<=0; hour2<=hour2+1; end else begin hour1<=hour1+1; end if((hour2==2)&&(hour1==3)) begin hour1<=0; hour2<=0; end end else begin minute2<=minute2+1; end end else begin minute1<=minute1+1; end end else begin
second2<=second2+1; end
end else begin second1<=second1+1; end end end
/////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////// always begin case(second1) 4'b0000: sec1<=8'hc0; //0 4'b0001: sec1<=8'hf9; //1 4'b0010: sec1<=8'ha4; //2 4'b0011: sec1<=8'hb0; //3 4'b0100: sec1<=8'h99; //4 4'b0101: sec1<=8'h92; //5 4'b0110: sec1<=8'h82; //6 4'b0111: sec1<=8'hf8; //7 4'b1000: sec1<=8'h80; //8 4'b1001: sec1<=8'h90; //9 default: sec1<=8'hc0;
endcase end //////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////// always begin case(second2) 4'b0000: sec2<=8'hc0; //0 4'b0001: sec2<=8'hf9; //1 4'b0010: sec2<=8'ha4; //2 4'b0011: sec2<=8'hb0; //3 4'b0100: sec2<=8'h99; //4 4'b0101: sec2<=8'h92; //5
default: sec2<=8'hc0;
endcase end //////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////// always begin case(minute1) 4'b0000: min1<=8'h40; //0 4'b0001: min1<=8'h79; //1 4'b0010: min1<=8'h24; //2 4'b0011: min1<=8'h30; //3 4'b0100: min1<=8'h19; //4 4'b0101: min1<=8'h12; //5 4'b0110: min1<=8'h02; //6 4'b0111: min1<=8'h78; //7 4'b1000: min1<=8'h00; //8 4'b1001: min1<=8'h10; //9 default: min1<=8'h40;
endcase end //////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////// always begin case(minute2) 4'b0000: min2<=8'hc0; //0 4'b0001: min2<=8'hf9; //1 4'b0010: min2<=8'ha4; //2 4'b0011: min2<=8'hb0; //3 4'b0100: min2<=8'h99; //4 4'b0101: min2<=8'h92; //5
default: min2<=8'hc0;
endcase end //////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////// always begin case(hour1) 4'b0000: hou1<=8'h40; //0 4'b0001: hou1<=8'h79; //1 4'b0010: hou1<=8'h24; //2 4'b0011: hou1<=8'h30; //3 4'b0100: hou1<=8'h19; //4 4'b0101: hou1<=8'h12; //5 4'b0110: hou1<=8'h02; //6 4'b0111: hou1<=8'h78; //7 4'b1000: hou1<=8'h00; //8 4'b1001: hou1<=8'h10; //9 default: hou1<=8'h40;
endcase end //////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////// always begin case(hour2) 4'b0000: hou2<=8'hc0; //0 4'b0001: hou2<=8'hf9; //1 4'b0010: hou2<=8'ha4; //2
default: hou2<=8'hc0;
endcase end //////////////////////////////////////////////////////////////////// endmodule
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