module Counter0_99(clk_50M,clr,cn,low_seg,high_seg);
input clk_50M,clr;
output cn;
output [7:0] low_seg;
output [7:0] high_seg;
wire cn;
wire [7:0] low_seg;
wire [7:0] high_seg;
wire clk_1Hz;
wire [3:0] high,low;
clk_div1Hz A1(.clk_50M(clk_50M),.clk_1Hz(clk_1Hz));
Twobits_count A2(.clk_1Hz(clk_1Hz),.clr(clr),.high(high),.low(low),.cn(cn));
decoder1 A3(.high(high),.high_seg(high_seg));
decoder2 A4(.low(low),.low_seg(low_seg));
endmodule
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