关键代码
module Accumulator
(
CLK,RSTn,Result
);
input CLK;
input RSTn;
output reg[7:0] Result;
always@(posedge CLK or negedge RSTn)
begin
if(!RSTn)
begin
// Result[7:4]<=0;
// Result[3:0]<=0;
end
else if(Result[3:0]==4'd9)
begin
Result[3:0]<=0;
Result[7:4]<=Result[7:4]+1'b1;
end
else
Result[3:0]<=Result[3:0]+1'b1;
end
endmodule
全部代码见附件
Counter.zip
(7.49 MB, 下载次数: 23)
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