里面有详细的设计过程包括代码、visio画的时序图
fpga源程序如下:
- module vga_ctrl(
- sclk,
- rst_n,
- hsync,
- vsync,
- rgb_data
- );
- input sclk;
- input rst_n;
- output hsync;
- output vsync;
- output [7:0]rgb_data;
- reg clk;
- reg hsync;
- reg vsync;
- reg [9:0]cnt_h;
- reg [9:0]cnt_v;
- reg [7:0]rgb_data;
- /* wire [7:0]out_data;
- reg [13:0]rd_addr; */
- /* my_pll my_pll_inst (
- .inclk0 ( sclk ),
- .c0 ( clk )
- );
- */
- always@(posedge sclk or negedge rst_n)
- if(rst_n==1'b0)
- clk<=0;
- else
- clk<=~clk;
-
-
-
- //cnt_h;
- always@(posedge clk or negedge rst_n)
- if(rst_n==1'b0)
- cnt_h<=0;
- else if(cnt_h==799)
- cnt_h<=0;
- else
- cnt_h<=cnt_h+1;
-
- always@(posedge clk or negedge rst_n)
- if(rst_n==1'b0)
- cnt_v<=0;
- else if(cnt_v==524&&cnt_h==799)
- cnt_v<=0;
- else if(cnt_h==799)
- cnt_v<=cnt_v+1;
-
- always@(posedge clk or negedge rst_n)
- if(rst_n==1'b0)
- hsync<=1;
- else if(cnt_h==95)
- hsync<=1;
- else if(cnt_h==799)
- hsync<=0;
-
- always@(posedge clk or negedge rst_n)
- if(rst_n==1'b0)
- vsync<=1;
- else if(cnt_h==799&&cnt_v==1)
- vsync<=1;
- else if(cnt_h==799&&cnt_v==524)
- vsync<=0;
-
-
- always@(posedge clk or negedge rst_n)
- if(rst_n==1'b0)
- rgb_data<=0;
- else if( cnt_h>=143&&cnt_h<243&&cnt_v>=34&&cnt_v<134)
- rgb_data<=8'b0011_1111;
- else if(cnt_h>=143&&cnt_h<783&&cnt_v>=34&&cnt_v<194)
- rgb_data<=8'b111_000_00;
- else if(cnt_h>=143&&cnt_h<783&&cnt_v>=194&&cnt_v<354)
- rgb_data<=8'b000_111_00;
- else if(cnt_h>=143&&cnt_h<783&&cnt_v>=354&&cnt_v<514)
- rgb_data<=8'b000_000_11;
- else
- rgb_data<=8'b0;
- /* my_ram my_ram_inst (
- .clock ( clk ),
- .data ( 0 ),
- .rdaddress ( rd_addr ),
- .wraddress ( 0 ),
- .wren ( 0 ),
- .q ( out_data )
- ); */
- /*
- always@(posedge clk or negedge rst_n)
- if(rst_n==1'b0)
- rd_addr<=0;
- else if(cnt_h>=143&&cnt_h<243&&cnt_v>=34&&cnt_v<134)
- begin
- if(rd_addr==9999)
- rd_addr<=0;
- else
- rd_addr<=rd_addr+1;
- end
- */
- endmodule
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