FPGA快速傅里叶变换（FFT）程序

ID:440209 · 发表于 2018-12-5 23:01

傅里叶变换

Module buterfly(out1_re,out1_im,out2_re,out2_im,in1_re,in1_im,in2_re,in2_im,clk);
Output[7:0] out1_re,out1_im,out2_re,out2_im;
Input[7:0] in1_re,in1_im,in2_re,in2_im;
Input clk;
reg[7:0] out1_re,out1_im,out2_re,out2_im;
reg[15:0]temp_re,temp_im;
reg[7:0]temp1,temp2;
function[15:0]mul;
input[7:0]in;
reg[13:0]str1;
reg[11:0]str2;
reg[10:0]str3;
reg[9:0]str4;
reg[15:0]mul1,mul2;
begin
assign str4=in<<1;
assign str3=str4<<2;
assign str2=str3<<1;
assign str1=str2<<2;
assign mul1=str4+str3;
assign mul2=str2+str1;
mul=mul1+mul2;
end
endfunction
always @(posdge clk)
begin
temp_re =mul(in2_re);
temp im =mul(in2_im);
temp1= temp_re[14:7-temp_im[14:7];
temp2= temp_re[14:7]+ temp_im[14:7];
out1_re= in1_re+temp1;
out1_im=in1_im+temp1;
out2_re=in1_re-temp2;
out2_im=in2_im-temp2;
end
endmodule

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ID:122941 · 发表于 2018-12-15 10:26

reg [7:0] out1_re,out1_im,out2_re,out2_im;怎么没见到这两个有赋值的地方?

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