FPGA的秒表程序设计（跑表模块+防抖模块+测试模块）

ID:353926 · 发表于 2019-4-9 09:52

防抖模块：

module button_scan(clk, bin, bout);
input clk;
input bin;
output bout;
reg bout;
parameter cnt = 200;
reg [ 1: 0] state = 0;
reg [31: 0] dcnt;
always@(posedge clk)
case(state)
0: begin //不稳定0
if(bin) state <= 1;
else state <= dcnt>=dcnt?2:0;
end
1: begin //稳定1
if(!bin)
begin
state <= 0;
dcnt <= 0;
end
end
2: begin //稳定0
if(bin)
begin
state <= 3;
dcnt <= 0;
end
end
3: begin //不稳定1
if(!bin) state <= 2;
else state <= dcnt>=dcnt?1:3;
end
endcase
always@(state)
case(state)
0: bout <= bout;
1: bout <= 1;
2: bout <= 0;
3: bout <= bout;
default: bout <= bout;
endcase
endmodule

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跑表模块：

module button(clk,sw,LED0,LED1,LED);
input clk;
input [3:0] sw;
output [7:0] LED0;
output [7:0] LED1;
output [7:0] LED;
reg [7:0] LED0;
reg [7:0] LED1;
reg [7:0] LED;
reg [31: 0] cnt0; //记时50 000 000个周期为一秒
reg [31: 0] cnt1;
reg [31: 0] cnt2;
reg [31: 0] cnt3;
reg [31: 0] cnt4;
reg [ 3: 0] codein0;
reg [ 3: 0] codein1;
reg [ 3: 0] codein2;
reg [ 2: 0] codein3;
reg codein4;
reg clk1;
reg be;
reg [23:0] t0,t1,t2,t3,t4,t5,t6,t7,t8,t9;
reg [7:0] aLED0;
reg [7:0] aLED1;
reg [7:0] aLED;
reg [3:0] p,q;
defparam sw0.cnt = 250;
defparam sw1.cnt = 250;
defparam sw2.cnt = 250;
defparam sw3.cnt = 250;
button_scan sw0(.clk(clk), .bin(sw[0]), .bout(bsw0));
button_scan sw1(.clk(clk), .bin(sw[1]), .bout(bsw1));
button_scan sw2(.clk(clk), .bin(sw[2]), .bout(bsw2));
button_scan sw3(.clk(clk), .bin(sw[3]), .bout(bsw3));
initial
begin
t0<=24'b1111_1111_1100_0000_1100_0000;
t1<=24'b1111_1111_1100_0000_1100_0000;
t2<=24'b1111_1111_1100_0000_1100_0000;
t3<=24'b1111_1111_1100_0000_1100_0000;
t4<=24'b1111_1111_1100_0000_1100_0000;
t5<=24'b1111_1111_1100_0000_1100_0000;
t6<=24'b1111_1111_1100_0000_1100_0000;
t7<=24'b1111_1111_1100_0000_1100_0000;
t8<=24'b1111_1111_1100_0000_1100_0000;
t9<=24'b1111_1111_1100_0000_1100_0000;
end
always@(posedge bsw0)
begin
be=~be;
end
always@(posedge bsw2)
begin
p<=p+1;
if(p<=9)
case(p)
0:t0<={LED,LED1,LED0};
1:t1<={LED,LED1,LED0};
2:t2<={LED,LED1,LED0};
3:t3<={LED,LED1,LED0};
4:t4<={LED,LED1,LED0};
5:t5<={LED,LED1,LED0};
6:t6<={LED,LED1,LED0};
7:t7<={LED,LED1,LED0};
8:t8<={LED,LED1,LED0};
9:t9<={LED,LED1,LED0};
endcase
else
p<=0;
end
always @(posedge bsw3)
begin
q<=q-1;
if(q<=9&&q>=0)
case(q)
0: {aLED,aLED1,aLED0}<=t0;
1: {aLED,aLED1,aLED0}<=t1;
2: {aLED,aLED1,aLED0}<=t2;
3: {aLED,aLED1,aLED0}<=t3;
4: {aLED,aLED1,aLED0}<=t4;
5: {aLED,aLED1,aLED0}<=t5;
6: {aLED,aLED1,aLED0}<=t6;
7: {aLED,aLED1,aLED0}<=t7;
8: {aLED,aLED1,aLED0}<=t8;
9: {aLED,aLED1,aLED0}<=t9;
endcase
else
q<=9;
end
always @(posedge clk)
begin
if(!bsw1)
begin
codein0<=0;
end
else
begin
if(cnt0>=50_000_0&&be)
begin
cnt0 <= 0;
if(codein0 >= 9)
begin
codein0 <= 0;
end
else
begin
codein0 <= codein0 + 1;
end
end
else
begin
cnt0 <= cnt0 + 1;
codein0 <= codein0;
end
end
end
always @(posedge clk)
begin
if(!bsw1)
begin
codein1<=0;
end
else
begin
if(cnt1>=50_000_00&&be)
begin
cnt1 <= 0;
if(codein1 >= 9)
begin
codein1 <= 0;
end
else
begin
codein1 <= codein1 + 1;
end
end
else
begin
cnt1 <= cnt1 + 1;
codein1 <= codein1;
end
end
end
always @(posedge clk)
begin
if(!bsw1)
begin
codein2<=0;
end
else
begin
if(cnt2>=50_000_000&&be)
begin
cnt2 <= 0;
if(codein2 >= 9)
begin
codein2 <= 0;
end
else
begin
codein2 <= codein2 + 1;
end
end
else
begin
cnt2 <= cnt2 + 1;
codein2 <= codein2;
end
end
end
always @(posedge clk)
begin
if(!bsw1)
begin
codein3<=0;
end
else
begin
if(cnt3>=500_000_000&&be)
begin
cnt3 <= 0;
if(codein3 >= 5)
begin
codein3 <= 0;
end
else
begin
codein3 <= codein3 + 1;
end
end
else
begin
cnt3 <= cnt3 + 1;
codein3 <= codein3;
end
end
end
always @(posedge clk)
begin
if(!bsw1)
begin
codein4<=0;
end
else
begin
if(cnt4>=3000_000_000&&be)
begin
cnt4 <= 0;
if(codein4 >= 1)
begin
codein4 <= 0;
end
else
begin
codein4 <= codein4 + 1;
end
end
else
begin
cnt4 <= cnt4 + 1;
codein4 <= codein4;
end
end
end
always @(codein0)
if(!bsw1)
begin
LED0<=aLED0;
end
else
begin
case(codein0)
4'h0: LED0 = 8'b1100_0000;
4'h1: LED0 = 8'b1111_1001;
4'h2: LED0 = 8'b1010_0100;
4'h3: LED0 = 8'b1011_0000;
4'h4: LED0 = 8'b1001_1001;
4'h5: LED0 = 8'b1001_0010;
4'h6: LED0 = 8'b1000_0010;
4'h7: LED0 = 8'b1111_1000;
4'h8: LED0 = 8'b1000_0000;
4'h9: LED0 = 8'b1001_0000;
default: LED0 = 8'b0111_1111;
endcase
end
always @(codein1)
if(!bsw1)
begin
LED1<=aLED1;
end
else
begin
case(codein1)
4'h0: LED1 = 8'b1100_0000;
4'h1: LED1 = 8'b1111_1001;
4'h2: LED1 = 8'b1010_0100;
4'h3: LED1 = 8'b1011_0000;
4'h4: LED1 = 8'b1001_1001;
4'h5: LED1 = 8'b1001_0010;
4'h6: LED1 = 8'b1000_0010;
4'h7: LED1 = 8'b1111_1000;
4'h8: LED1 = 8'b1000_0000;
4'h9: LED1 = 8'b1001_0000;
default: LED1 = 8'b0111_1111;
endcase
end
always @(codein2)
if(!bsw1)
begin
LED[3:0]<=aLED[3:0];
end
else
begin
case(codein2)
4'h0: LED[3:0] = 4'b1111;
4'h1: LED[3:0] = 4'b1110;
4'h2: LED[3:0] = 4'b1101;
4'h3: LED[3:0] = 4'b1100;
4'h4: LED[3:0] = 4'b1011;
4'h5: LED[3:0] = 4'b1010;
4'h6: LED[3:0] = 4'b1001;
4'h7: LED[3:0] = 4'b1000;
4'h8: LED[3:0] = 4'b0111;
4'h9: LED[3:0] = 4'b0110;
default: LED[3:0] = 8'b0000;
endcase
end
always @(codein3)
if(!bsw1)
begin
LED[6:4]<=aLED[6:4];
end
else
begin
case(codein3)
3'h0: LED[6:4] = 4'b111;
3'h1: LED[6:4] = 4'b110;
3'h2: LED[6:4] = 4'b101;
3'h3: LED[6:4] = 4'b100;
3'h4: LED[6:4] = 4'b011;
3'h5: LED[6:4] = 4'b010;
default: LED[6:4] = 8'b000;
endcase
end
always @(codein4)
if(!bsw1)
begin
LED[7]<=aLED[7];
end
else
begin
case(codein4)
1'h0: LED[7] = 1'b1;
1'h1: LED[7] = 1'b0;
default: LED[7] = 1'b0;
endcase
end
endmodule

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测试模块：

`timescale 1ms/1ms
`include”button.v”
module buttontest;
reg clk;
reg bsw0;
reg bsw1;
reg bsw2;
reg bsw3;
reg [7:0] LED0;
reg [7:0] LED1;
reg [7:0] LED;
initial begin
bsw0=1;bsw3=1;
#175 bsw0=0; #75 bsw0=1;
#20 bsw2=0; # 20 bsw2=1;
#20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; # 20 bsw2=1;
# 20 bsw2=0; #20 bsw2=1;
#600 bsw3=0 ; #610 bsw3=1;
# 10000 $stop;
always #5 clk=~clk;
end
button button(clk,bsw0,bsw1,bsw2,bsw3,LED0,LED1,LED);
endmodule

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FPGA的秒表程序设计（ 跑表模块+防抖模块+测试模块）

FPGA的秒表程序设计（跑表模块+防抖模块+测试模块）