module QQ(clk,clk_out);
input clk;
output reg clk_out;
reg [31:0] cnt;
always@(posedge clk)
begin
if(cnt<=5000000)
begin
clk_out<=0;
cnt<=cnt+1;
end
elseif((cnt>2500000)&&(cnt<5000000))
begin
clk_out<=1;
cnt<=cnt+1;
end
else
begin
clk_out<=1;
cnt<=0;
end
end
endmodule
module QQQ(clk,count_c,counter_out);
input clk;
output reg count_c;
output reg [7:0] counter_out;
reg current_state;
reg next_state;
always@( current_state)
begin
case(current_state)
1'b0:
begin
count_c=0; if(counter_out<58)
next_state=0;
else
next_state=1;
end
1'b1:
begin
next_state=0;
count_c=1;
end
default:
begin
end
endcase
end
always@(posedge clk)
begin
current_state<=next_state;
if(counter_out<58)
counter_out<=counter_out+1;
else
counter_out<=0;
end
endmodule
module smg(
input clk,
input count_c,
input [7:0]counter_out,
output [7:0]duan,//数码管段选
output [2:0]wei//数码管位选
);
reg [32:0] cnt;// 时钟分频计数器
parameter system_clk = 50_000_000;
localparam cnt1_MAX = system_clk/1000/2-1;
reg [14:0] cnt1; //分频计数器
reg clk_1k; //扫描时钟，1KHz
reg [2:0]flag_wei; //数码管位选
reg [7:0]flag_duan; //数码管段选
reg [3:0]disp_data; //单位显示数据缓存
reg [32:0]flagf1;
reg [32:0]flagm1;
reg [32:0]flagm2;
//1KHz时钟分频计数器
always@(posedge clk)
begin
if(cnt1==cnt1_MAX)cnt1<=0;
else cnt1<=cnt1+1'b1;
end
//得到1KHz时钟
always@(posedge clk)
if(cnt1==cnt1_MAX)
clk_1k<=~clk_1k;
always@(posedge clk)
begin
if(clk)
begin
flagm2<=counter_out/10;//个位
flagm1<=counter_out%10;//十位
flagf1<=count_c;
end
end
//位选信号控制
always@(posedge clk_1k)
if(flag_wei == 3'd5)
flag_wei<=3'd0;
else
flag_wei<=flag_wei+1'b1;
//根据不同的数码管位选择不同的待显示数据
always@(*)
begin
case(flag_wei)
3'd0:disp_data<=0;
3'd1:disp_data<=0;
3'd2:disp_data<=0;
3'd3:disp_data<=flagf1;
3'd4:disp_data<=flagm2;
3'd5:disp_data<=flagm1;
default :disp_data<=4'd0;
endcase
end
//显示小数点,分割时分秒
always @ (*)
begin
case(flag_wei)
0: flag_duan[7] = 1'b1;
1: flag_duan[7] = 1'b1;
2: flag_duan[7] = 1'b1;
3: flag_duan[7] = 1'b1;
4: flag_duan[7] = 1'b1;
5: flag_duan[7] = 1'b1;
default: flag_duan[7] = 1'b1;
endcase
end
//数据译码，将待显示数据翻译为符合数码管显示的编码
always@(*)
begin
case(disp_data)
4'd0: flag_duan[6:0]=7'b1000000;
4'd1: flag_duan[6:0]=7'b1111001;
4'd2: flag_duan[6:0]=7'b0100100;
4'd3: flag_duan[6:0]=7'b0110000;
4'd4: flag_duan[6:0]=7'b0011001;
4'd5: flag_duan[6:0]=7'b0010010;
4'd6: flag_duan[6:0]=7'b0000010;
4'd7: flag_duan[6:0]=7'b1111000;
4'd8: flag_duan[6:0]=7'b0000000;
4'd9: flag_duan[6:0]=7'b0010000;
default : flag_duan[6:0]=7'b1111111;
endcase
end
assign wei = flag_wei;
assign duan = flag_duan;
endmodule
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