VHDL设计洗衣机电路，暂停和开始键，待机2秒正转8秒待机2秒反转8秒待机2秒，循环3次结束后响铃3秒结束。
按键对照表:
CLK_50M 91
start1 KEY1 11
Zhanting KEY2 25
led_zheng LED1 39
led_fan LED2 31
led_stop LED3 3
beep 7
WEI[0] SEG_C1 98
WEI[1] SEG_C2 99
WEI[2] SEG_C3 86
WEI[3] SEG_C4 87
LED7[0] G 103
LED7[1] F 101
LED7[2] E 106
LED7[3] D 110
LED7[4] C 104
LED7[5] B 111
LED7[6] A 100
vhdl源程序如下:- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- ENTITY xiyiji IS
- PORT( CLK_50M,Zhanting,start1:IN STD_LOGIC;
- WEI,time_1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- LED7:OUIS
- COMPONENT div
- PORT(CLK_IN:IN STD_LOGIC;T STD_LOGIC_VECTOR(6 DOWNTO 0);
- led_zheng,led_fan,led_stop,beep:out std_logic
- );
- END ENTITY xiyiji;
- ARCHITECTURE BHV_0 OF xiyiji
- CLK_OUT:OUT STD_LOGIC);
- END COMPONENT;
-
- COMPONENT decoder
- PORT(D_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
- END COMPONENT;
-
- COMPONENT keshe
- PORT(
- emergency,clk,start: IN STD_LOGIC;
- counter,times :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- zheng,fan,stop,ring:OUT STD_LOGIC
- );
- END COMPONENT;
-
- SIGNAL H:STD_LOGIC;
- SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0);
-
- BEGIN
- U1:div PORT
- MAP(CLK_IN=>CLK_50M,CLK_OUT=>H);
- U2:keshe PORT
- MAP(CLK=>H,counter=>S,emergency=>Zhanting,start=>start1,
- ring=>beep,times=>time_1,zheng=>led_zheng,fan=>led_fan,stop=>led_stop);
- U3:decoder PORT
- MAP(D_IN=>S,DOUT=>LED7);
- WEI<="0111";
-
- END BHV_0;
全部资料51hei下载地址：
keshe.zip
(3.46 MB, 下载次数: 41)
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