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- //******模块一:分频器*****************//
- /*en1为使能端,clk为输入频率,outdiv(0-9)为输出频率,
- outdiv(0)为不进行分频,outdiv(1)进行2分频,
- outdiv(2)进行3分频,outdiv(3)进行4分频,
- outdiv(4)进行5分频,outdiv(5)进行6分频,
- outdiv(6)进行7分频,outdiv(7)进行8分频,
- outdiv(8)进行9分频,outdiv(9)进行10分频。*/
- library ieee;
- use ieee.std_logic_1164.all;
- entity FPQ is
- port(clk,en1: in std_logic;
- outdiv : out std_logic_vector(9 downto 0));
- end FPQ;
- architecture bh of FPQ is
- begin
- process(en1,clk)
- variable t1 : integer range 0 to 2;
- variable t2 : integer range 0 to 3;
- variable t3 : integer range 0 to 4;
- variable t4 : integer range 0 to 5;
- variable t5 : integer range 0 to 6;
- variable t6 : integer range 0 to 7;
- variable t7 : integer range 0 to 8;
- variable t8 : integer range 0 to 9;
- variable t9 : integer range 0 to 10;
- begin
- outdiv(0) <= clk;
- if clk'event and clk = '1' then
- if en1 = '1' then
- if (t1 >= 2) then t1:=0;outdiv(1)<='0';
- elsif t1<1 then outdiv(1)<='0';
- else outdiv(1) <= '1';
- end if;
- t1:=t1+1;
- if (t2 >= 3) then t2:=0;outdiv(2)<='0';
- elsif t2<2 then outdiv(2)<='0';
- else outdiv(2) <= '1';
- end if;
- t2:=t2+1;
- if (t3 >= 4) then t3:=0;outdiv(3)<='0';
- elsif t3<2 then outdiv(3)<='0';
- else outdiv(3) <= '1';
- end if;
- t3:=t3+1;
- if (t4 >= 5) then t4:=0;outdiv(4)<='0';
- elsif t4<3 then outdiv(4)<='0';
- else outdiv(4) <= '1';
- end if;
- t4:=t4+1;
- if (t5 >= 6) then t5:=0;outdiv(5)<='0';
- elsif t5<3 then outdiv(5)<='0';
- else outdiv(5) <= '1';
- end if;
- t5:=t5+1;
- if (t6 >= 7) then t6:=0;outdiv(6)<='0';
- elsif t6<4 then outdiv(6)<='0';
- else outdiv(6) <= '1';
- end if;
- t6:=t6+1;
- if (t7 >= 8) then t7:=0;outdiv(7)<='0';
- elsif t7<4 then outdiv(7)<='0';
- else outdiv(7) <= '1';
- end if;
- t7:=t7+1;
- if (t8 >= 9) then t8:=0;outdiv(8)<='0';
- elsif t8<5 then outdiv(8)<='0';
- else outdiv(8) <= '1';
- end if;
- t8:=t8+1;
- if (t9 >= 10) then t9:=0;outdiv(9)<='0';
- elsif t9<5 then outdiv(9)<='0';
- else outdiv(9) <= '1';
- end if;
- t9:=t9+1;
- end if;
- end if;
- end process;
- end bh;
-
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-
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-
-
- //***********模块二:频率选择器**************//
- /*P0、P1、P2、P3为频率选择信号,indiv(0-9)为分频器分频之后的频率信号,
- outclk为要选择的频率。
- 当p(3-0)为"0000"时,outclk为indiv(0);当p(3-0)为"0001"时,outclk为indiv(1);
- 当p(3-0)为"0010"时,outclk为indiv(2);当p(3-0)为"0011"时,outclk为indiv(3);
- 当p(3-0)为"0100"时,outclk为indiv(4);当p(3-0)为"0101"时,outclk为indiv(5);
- 当p(3-0)为"0110"时,outclk为indiv(6);当p(3-0)为"0111"时,outclk为indiv(7);
- 当p(3-0)为"1000"时,outclk为indiv(8);当p(3-0)为"1001"时,outclk为indiv(9);
- 当p(3-0)为其它时,outclk为indiv(0)。*/
- library ieee;
- use ieee.std_logic_1164.all;
- entity PLXZQ is
- port(p: in std_logic_vector(3 downto 0);
- indiv : in std_logic_vector(9 downto 0);
- outclk : out std_logic);
- end PLXZQ;
- architecture bh1 of PLXZQ is
- begin
- process(p,indiv)
- begin
- case p is
- when "0000" => outclk <= indiv(0);
- when "0001" => outclk <= indiv(1);
- when "0010" => outclk <= indiv(2);
- when "0011" => outclk <= indiv(3);
- when "0100" => outclk <= indiv(4);
- when "0101" => outclk <= indiv(5);
- when "0110" => outclk <= indiv(6);
- when "0111" => outclk <= indiv(7);
- when "1000" => outclk <= indiv(8);
- when "1001" => outclk <= indiv(9);
- when others => outclk <= indiv(0);
- end case;
- end process;
- end bh1;
-
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-
-
-
-
- //***********模块三:方向锁存器**************//
- /*Zz、Fz、Tz为方向和开关信号,Modxz为六拍和三拍选择切换信号,
- outctrl为输出的控制信号。
- 当Modxz为1时,为六拍;当Modxz为0时,为双三拍。
- 当Tz为1时,为停止电机,当Tz为0时,为启动电机。
- 当Zz为1、Fz为0时,为电机正转,
- 当Zz为0、Fz为1时,为电机反转,
- 当Zz为1、Fz为1时,为电机停止,
- 当Zz为0、Fz为0时,为电机停止。
- outctrl(0)对应Tz;outctrl(1)对应Fz;
- outctrl(2)对应Zz;outctrl(3)对应Modxz。*/
- library ieee;
- use ieee.std_logic_1164.all;
- entity FXSCQ is
- port(modxz,zz,fz,tz: in std_logic;
- outctrl: out std_logic_vector(3 downto 0));
- end FXSCQ;
- architecture bh2 of FXSCQ is
- begin
- process(modxz,zz,fz,tz)
- begin
- outctrl(0) <= tz;
- outctrl(1) <= fz;
- outctrl(2) <= zz;
- outctrl(3) <= modxz;
- if zz = '1' and fz = '1' then
- outctrl(0) <= '1';
- elsif zz = '0' and fz = '0' then
- outctrl(0) <= '1';
- end if;
- end process;
- end bh2;
-
-
-
-
-
-
- //***********模块四:中央控制器**************//
- /*inclk为经过频率选择器选择之后的输入频率,
- inctrl为经过方向锁存器之后的输入控制信号,
- outDj为三相电机的的三相电压,
- 当inctrl为“0100”时,电机为双三相正转;
- 当inctrl为“0010”时,电机为双三相反转;
- 当inctrl为“1100”时,电机为单六相正转;
- 当inctrl为“1010”时,电机为单六相正转;
- 当inctrl为“xxx1”时,电机停止。*/
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity CPU is
- port(inclk: in std_logic;
- inctrl: in std_logic_vector(3 downto 0);
- outDJ: out std_logic_vector(2 downto 0));
- end CPU;
- architecture bh3 of CPU is
- signal Tmp : std_logic_vector(2 downto 0);
- begin
- process(inclk,inctrl)
- begin
- if inclk'event and inclk = '1' then
- if inctrl = "1100" then
- if Tmp = 6 then
- Tmp <= "001";
- else
- Tmp <= Tmp+1;
- end if;
- elsif inctrl = "1010" then
- if Tmp = 1 then
- Tmp <= "110";
- else
- Tmp <= Tmp-1;
- end if;
- elsif inctrl = "1000" then
- Tmp <= "000";
- elsif inctrl = "0100" then
- if Tmp = 6 then
- Tmp <= "010";
- else
- Tmp <= Tmp+2;
- end if;
- elsif inctrl = "0010" then
- if Tmp = 2 then
- Tmp <="110";
- else
- Tmp <= Tmp-2;
- end if;
- elsif inctrl = "0000" then
- Tmp <= "000";
- end if;
- end if;
- end process;
- with Tmp select
- outDJ <= "001" when "001",
- "011" when "010",
- "010" when "011",
- "110" when "100",
- "100" when "101",
- "101" when "110",
- "000" when others;
- end bh3;
-
-
-
- //***********模块五:译码器**************//
- /*xyk(3-0)为输入信号,输入数值,dnf(8-0)为输出控制数码管信号。
- //dnf(8)为数码管的位选信号。
- 当xyk为“0000”时,dnf输出为“100111111”, 数码管显示‘0’;
- 当xyk为“0001”时,dnf输出为“100000110”, 数码管显示‘1’;
- 当xyk为“0010”时,dnf输出为“101011011”, 数码管显示‘2’;
- 当xyk为“0011”时,dnf输出为“101001111”, 数码管显示‘3’;
- 当xyk为“0100”时,dnf输出为“101100110”, 数码管显示‘4’;
- 当xyk为“0101”时,dnf输出为“100101001”, 数码管显示‘5’;
- 当xyk为“0110”时,dnf输出为“101111101”, 数码管显示‘6’;
- 当xyk为“0111”时,dnf输出为“100000111”, 数码管显示‘7’;
- 当xyk为“1000”时,dnf输出为“101111111”, 数码管显示‘8’;
- 当xyk为“1001”时,dnf输出为“101100111”, 数码管显示‘9’;
- 当xyk为其它时,dnf输出为“100111111”, 数码管显示‘0’。*/
- library ieee;
- use ieee.std_logic_1164.all;
- entity YMQ is
- port(xyk: in std_logic_vector(3 downto 0);
- dnf: out std_logic_vector(8 downto 0));
- end YMQ;
- architecture bh4 of YMQ is
- begin
- process(xyk)
- begin
- case xyk is
- when "0000" => dnf <= "100111111";
- when "0001" => dnf <= "100000110";
- when "0010" => dnf <= "101011011";
- when "0011" => dnf <= "101001111";
- when "0100" => dnf <= "101100110";
- when "0101" => dnf <= "100101001";
- when "0110" => dnf <= "101111101";
- when "0111" => dnf <= "100000111";
- when "1000" => dnf <= "101111111";
- when "1001" => dnf <= "101100111";
- when others => dnf <= "100111111";
- end case;
- end process;
- end bh4;
-
-
-
-
- //********总体:模块的例化*************//
- library ieee;
- use ieee.std_logic_1164.all;
- entity zong is
- port(clk0,en0,Modxz0,Zz0,Fz0,Tz0 : in std_logic;
- P0 : in std_logic_vector(3 downto 0);
- DNF0 : out std_logic_vector(8 downto 0);
- OutDJ0 : out std_logic_vector(2 downto 0));
- end zong;
- architecture bh0 of zong is
- component FPQ
- port(clk,en1: in std_logic;
- outdiv : out std_logic_vector(9 downto 0));
- end component;
- component PLXZQ
- port(p: in std_logic_vector(3 downto 0);
- indiv : in std_logic_vector(9 downto 0);
- outclk : out std_logic);
- end component;
- component YMQ
- port(xyk: in std_logic_vector(3 downto 0);
- dnf: out std_logic_vector(8 downto 0));
- end component;
- component CPU
- port(inclk: in std_logic;
- inctrl: in std_logic_vector(3 downto 0);
- outDJ: out std_logic_vector(2 downto 0));
- end component;
- component FXSCQ
- port(modxz,zz,fz,tz: in std_logic;
- outctrl: out std_logic_vector(3 downto 0));
- end component;
- signal DX1 :std_logic;
- signal DX2 :std_logic_vector(9 downto 0);
- signal DX3 :std_logic_vector(3 downto 0);
- begin
- U0 : FPQ port map (clk0,en0,DX2);
- U1 : PLXZQ port map (p0,DX2,DX1);
- U2 : YMQ port map (p0,dnf0);
- U3 : CPU port map (DX1,DX3,OutDJ0);
- U4 : FXSCQ port map (Modxz0,Zz0,Fz0,Tz0,DX3);
- end bh0;
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