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1、设计并用 ISP1032 实现一个电子钟。电子钟具有下述功能：
a) 试验台上的 6 个数码管显示时、分、秒。
b) 能使电子钟复位（清零）。
c) 能启动或者停止电子钟运行。
d) 再电子钟停止运行状态下，能够修改时、分、秒的值。
e) 具有报时功能，整点时喇叭鸣叫。
2、要求整个设计分为若干模块。顶层模块用原理图设计，底层模块用 VHDL 语言设计。 3、在试验箱上调试设计。
模块Ⅰ：顶层模块 clock
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
------------------------------时钟主体部分---------------------------
ENTITY clock is
port(clk,clr,adj,clk1 : in std_logic; -----------clk 为 5KHZ 的时钟信号，clr 为清零信号，adj 为置数脉冲，clk1 为以 50KHZ 时钟信号控制响铃
choice : in std_logic; ---------用来选择时钟状态的脉冲信号
lighthour : out std_logic_vector(10 downto 0);
lightmin : out std_logic_vector(7 downto 0);
lightsec : out std_logic_vector(7 downto 0); -------对小时，分钟和秒的输出信号
ring : out std_logic); -------响铃信号
attribute LOC : string;
attribute LOC of RING : signal is "p74";
attribute LOC of CHOICE : signal is "p54";
attribute LOC of LIGHTHOUR : signal is "p9 p41 p6 p8 p12 p68 p5 p60 p10 p52 p56";
attribute LOC of LIGHTMIN : signal is "p32 p48 p33 p79 p18 p70 p46 p83";
attribute LOC of LIGHTSEC : signal is "p4 p14 p75 p37 p71 p47 p50 p29";
attribute LOC of CLK : signal is "p20";
attribute LOC of CLK1 : signal is "p82";
attribute LOC of ADJ : signal is "p15";
attribute LOC of CLR : signal is "p39"; --------锁定管脚
end clock;
---------------------------时钟的结构体部分--------------------------
ARCHITECTURE behavioral of clock is
component counter_60
port(clock : in std_logic;
clk_1s : in std_logic;
adjust : in std_logic;
clr : in std_logic;
load : in std_logic;
s1 : out std_logic_vector(3 downto 0);
s10 : out std_logic_vector(3 downto 0);
co : out std_logic);
end component; -------对模 60 计数器的例化
component counter_24
port(clock : in std_logic;
clk_1s : in std_logic;
adjust : in std_logic;
clr : in std_logic;
load : in std_logic;
s1 : out std_logic_vector(3 downto 0);
s10 : out std_logic_vector(6 downto 0));
end component; ---------对模 24 计数器的例化
signal sec,a:std_logic; ---------通过 2 分频产生一周期 1s 的 sec 信号
signal l1,l2,l3:std_logic; ---------通过 l1，l2，l3 来判定对时，分，秒的修改
signal c1,c2:std_logic; ---------低位向高位的进位信号，c1 为从秒向分的进位，c2 为从分向时的进位
signal load:std_logic_vector(1 downto 0);
signal temp:integer range 0 to 2499;
signal temp1:integer range 0 to 95; --------计数信号
signal sec_temp:std_logic_vector(7 downto 0); -----对秒的暂存信号
------------------------------基本时钟进程---------------------------
begin
u1 : counter_60 port map (sec,sec,adj,clr,l1,sec_temp(3 downto 0),sec_temp(7 downto 4),c1);
u2 : counter_60 port map (c1,sec,adj,clr,l2,lightmin(3 downto 0),lightmin(7 downto 4),c2);
u3 : counter_24 port map (c2,sec,adj,clr,l3,lighthour(3 downto 0),lighthour(10 downto 4));
lightsec(7 downto 0)<=sec_temp(7 downto 0); -----3 句例化语句构成了基本的时钟系统
--------------------------时钟的状态转换进程-----------------------
process (choice)
begin
if (choice'event and choice='1') then
case load is
when "00" => l1<='0'; ---------时钟的正常运行状态
l2<='0';
l3<='0';
load<="01";
when "01" => l1<='0'; -----此状态下对小时进行修改，即 l3=‘1’
l2<='0';
l3<='1';
load<="10";
when "10" => l1<='0'; -----此状态下对分钟进行修改，即 l2=‘1’
l2<='1';
l3<='0';
load<="11";
when others => l1<='1'; -----此状态下对 秒 进行修改，即 l1=‘1’
l2<='0';
l3<='0';
load<="00";
end case;
end if;
end process;
----------------------------1s 计数进程------------------------------
process(clk)
begin
if (clk'event and clk='1') then
if (temp=2499) then
temp <= 0;
sec<=not sec;
else
temp <= temp+1;
end if;
end if;
end process; --------基本 1s 二分频计数器
-------------------------------响铃进程------------------------------
process(clk1)
begin
if(clk1'event and clk1='1') then
if (temp1=95) then
temp1<=0;
a<=not a;
else
temp1<=temp1+1;
end if;
end if;
end process;
ring<=a when (c2='1' and sec_temp<10 and sec='1') else
'0';
end behavioral;
---------通过 sec 的控制产生间断的整点响铃，铃声为高音 1
模块Ⅱ：模块 counter_60
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------计数器主体部分----------------------------
entity counter_60 is
port (clock : in std_logic; ------计数信号，即低位的进位信号或时钟脉冲信号
clk_1s : in std_logic; -------周期 1s 的时钟信号
adjust : in std_logic; -------调表置数信号
clr : in std_logic; --------清零信号
load : in std_logic; -----------判定信号，判定当前计数器是否处于被修改状态
s1 : out std_logic_vector(3 downto 0); -------计数器的个位输出（4 位）
s10 : out std_logic_vector(3 downto 0); --------计数器的十位输出（4 位）
co : out std_logic --------本位向高位进位信号
);
end counter_60;
------------------------------------计数器的结构体部分----------------------------------------
architecture behavioral of counter_60 is
signal s1_temp: std_logic_vector(3 downto 0); ------计数器的个位暂存信号
signal s10_temp : std_logic_vector(3 downto 0); ------计数器的十位暂存信号
signal clk,co_temp : std_logic; -------脉冲控制信号
begin
clk<=clock when load='0' else
adjust;
---------通过脉冲控制信号来控制当前正常运行或调表置数
--------------------------------------模 60 计数进程--------------------------------------------
process (clk,clr)
begin
if (clr='1') then
s1_temp <= "0000";
s10_temp <= "0000";
elsif (clk'event and clk='1')then
if (s1_temp=9) then
s1_temp <= "0000";
if (s10_temp=5) then
s10_temp <= "0000";
co_temp<='1';
else
co_temp<='0';
s10_temp <= s10_temp+1;
end if;
else
co_temp<='0';
s1_temp <= s1_temp+1;
end if;
end if;
end process;
-----------------------------输出及显示------------------------------
s1 <= s1_temp when (clk_1s='1'or load='0') else
"1111";
s10 <= s10_temp when (clk_1s='1' or load='0') else
"1111";
------通过 1s 时钟信号来控制在调表状态下 对应的输出灯管 进行闪烁
co <= co_temp when (load='0') else
'0';
------当计数器处于被修改状态时不产生进位
end behavioral;
模块Ⅲ：模块 counter_24
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------计数器主体部分---------------------------
entity counter_24 is
port(clock : in std_logic; -----计数信号，即低位的进位信号
clk_1s : in std_logic; -------周期 1s 的时钟信号
adjust : in std_logic; --------调表置数信号
clr : in std_logic; --------清零信号
load : in std_logic; --------判定信号，判定当前计数器是否处于被修改状态
s1 : out std_logic_vector(3 downto 0); -------计数器的个位输出（4 位）
s10 : out std_logic_vector(6 downto 0));
--------计数器的十位输出（由于需 7 段译码故用 7 位）
end counter_24;
------------------------------------计数器的结构体部分----------------------------------------
architecture behavioral of counter_24 is
signal s1_temp : std_logic_vector(3 downto 0); -------计数器的个位暂存信号
signal s10_temp : std_logic_vector(1 downto 0); ------计数器的十位暂存信号
signal clk : std_logic; --脉冲控制信号
begin
clk<=clock when load='0' else
adjust; -------通过脉冲控制信号来控制当前正常运行或调表置数
---------------------------------------模 24 计数进程-------------------------------------------
process (clk,clr)
begin
if (clr='1') then
s1_temp <= "0000";
s10_temp <= "00";
elsif (clk'event and clk='1') then
if (s1_temp=3 and s10_temp=2) then
s1_temp <= "0000";
s10_temp <= "00";
elsif (s1_temp=9) then
s1_temp<="0000";
s10_temp<=s10_temp+1;
else
s1_temp <= s1_temp+1;
end if;
end if;
end process;
----------------------------------7 段译码和输出显示进程------------------------------------
process(s10_temp)
begin
if (clk_1s='1' or load='0') then
case s10_temp is
when "00" => s10<="1111110";
when "01" => s10<="0110000";
when "10" => s10<="1101101";
when others => null;
end case;
else
s10<="0000000";
end if;
end process;
s1 <= s1_temp when (clk_1s='1' or load='0') else
"1111";
--------通过 1s 时钟信号来控制在调表状态下 对应的输出灯管 进行闪烁
end behavioral;
以上代码 word格式:
数字电子钟代码.rar
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