基于FPGA的交通灯设计 附分频主控译码VHDL源程序

附录

分频器模块程序：
48分频：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fenpin2 IS
PORT(         
      CLK24M : IN  STD_LOGIC;
      CLK500k: OUT STD_LOGIC );
END fenpin2;
ARCHITECTURE BEHAV OF fenpin2 IS
  SIGNAL  COUNTER : INTEGER RANGE 0 TO 23;
  SIGNAL  CLK: STD_LOGIC;

  BEGIN
    PROCESS(CLK24M)  
    BEGIN            
      IF CLK24M'EVENT AND CLK24M='1' THEN
        IF COUNTER=23 THEN
              CLK<= NOT CLK;
              COUNTER <= 0;
        ELSE  COUNTER <= COUNTER+1;
                            END IF;
      END IF;
    END PROCESS;
   CLK500k <= CLK;
END;  
500000分频：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fenpin3 IS
PORT(         
      CLK500k : IN  STD_LOGIC;
      CLK1hz: OUT STD_LOGIC );
END;
ARCHITECTURE BEHAV OF fenpin3 IS
  SIGNAL  COUNTER : INTEGER RANGE 0 TO 249999;
  SIGNAL  CLK: STD_LOGIC;
  BEGIN
    PROCESS(CLK500k)  
    BEGIN            
      IF CLK500k'EVENT AND CLK500k='1' THEN
        IF COUNTER=249999 THEN
                                   COUNTER<=0;
              CLK<= NOT CLK;
        ELSE  COUNTER <= COUNTER+1;
                            END IF;
      END IF;
    END PROCESS;
   CLK1hz <= CLK;
END;
24999分频：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fenpin1 IS
PORT(         
      CLK500k : IN  STD_LOGIC;
      CLK10hz: OUT STD_LOGIC );
END;
ARCHITECTURE BEHAV OF fenpin1 IS
  SIGNAL  COUNTER : INTEGER RANGE 0 TO 24999;
  SIGNAL  CLK: STD_LOGIC;
  BEGIN
    PROCESS(CLK500k)  
    BEGIN            
      IF CLK500k'EVENT AND CLK500k='1' THEN
        IF COUNTER=24999 THEN
                                   COUNTER<=0;
              CLK<= NOT CLK;
        ELSE  COUNTER <= COUNTER+1;
                            END IF;
      END IF;
    END PROCESS;
   CLK10hz <= CLK;
END;
主控器程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zkq IS
PORT
(CLOCK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
NUMA,NUMB: OUT INTEGER RANGE 0 TO 40;
RedA,GreenA,YellowA: OUT STD_LOGIC;
RedB,GreenB,YellowB: OUT STD_LOGIC
);
END;
ARCHITECTURE CONTROL OF zkq IS
SIGNAL COUNTNUM: INTEGER RANGE 0 TO 80;
BEGIN
PROCESS(CLOCK,RESET)
BEGIN
  IF RESET='1' THEN
    COUNTNUM<=0;
  ELSIF RISING_EDGE(CLOCK) THEN
    IF COUNTNUM=79 THEN
      COUNTNUM<=0;
    ELSE
      COUNTNUM<=COUNTNUM+1;
   END IF;
  END IF;
END PROCESS;
PROCESS(CLOCK)
BEGIN
   IF RISING_EDGE(CLOCK) THEN
              IF RESET='1' THEN
                  RedA<='1';
                            RedB<='1';
         ELSIF COUNTNUM<=34 THEN
         NUMA<=35-COUNTNUM;
         RedA<='0';
         GreenA<='1';
         YellowA<='0';
       ELSIF (COUNTNUM<=39) THEN
         NUMA<=40-COUNTNUM;
         RedA<='0';
         GreenA<='0';
         YellowA<='1';
       ELSE
         NUMA<=80-COUNTNUM;
         RedA<='1';
         GreenA<='0';
         YellowA<='0';
       END IF;
       IF COUNTNUM<=39 THEN
         NUMB<=40-COUNTNUM;
         RedB<='1';
         GreenB<='0';
         YellowB<='0';
       ELSIF COUNTNUM<=74 THEN
         NUMB<=75-COUNTNUM;
         RedB<='0';
         GreenB<='1';
         YellowB<='0';
       ELSE
         NUMB<=80-COUNTNUM;
         RedB<='0';
         GreenB<='0';
         YellowB<='1';
       END IF;
     END IF;
  END PROCESS;
END;
提取显示值程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port
(
  CLK:IN std_logic;
  numin:in integer range 0 to 40;
  numa,numb:out integer range 0 to 9
);
end;
architecture bhv of xianshi is
begin
process(CLK)
begin
if rising_edge(CLK) then
if numin=40 then
numa <= 4;
numb <= 0;
elsif numin>=30 then
numa <=3;
numb <=numin-30;
elsif numin>=20 then
numa <=2;
numb <=numin-20;
elsif numin>=10 then
numa <=1;
numb <=numin-10;
else
numa <=0;
numb <=numin;
end if;
end if;
end process;
end;
动态扫描程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dongtai is
port(
  AH,AL,BH,BL:in std_logic_vector(3 downto 0);
  clk:in std_logic;
  q:buffer std_logic_vector(2 downto 0);
  dout:out std_logic_vector(3 downto 0)
);
end;
architecture bhv of dongtai is
signal qin:integer range 7 downto 0;
begin
p1:process(clk)
begin
if(clk'event and clk='1') then
if qin>3 then
qin<=0;
else
qin<=qin+1;
end if;
end if;
end process p1;
p2: process(qin,AL,AH,BH,BL)
begin
case qin is
when 0 => dout<=AH(3 downto 0);q<="111";
when 1 => dout<=AL(3 downto 0);q<="110";
when 2 => dout<=BH(3 downto 0);q<="011";
when 3 => dout<=BL(3 downto 0);q<="010";
when others =>null;
end case;
end process p2;
end;
译码器程序：
library ieee;
use ieee.std_logic_1164.all;
entity smxs is
port
(
dout:in std_logic_vector(3 downto 0);
led7s:out std_logic_vector(6 downto 0)
);
end;
architecture bhv of smxs is
begin
process(dout)
begin
   case dout is
   when "0000" => led7s <="0111111";
   when "0001" => led7s <="0000110";
   when "0010" =>  led7s <= "1011011" ;
   when "0011" =>  led7s <= "1001111" ;
   when "0100" =>  led7s <= "1100110" ;
   when "0101" =>  led7s <= "1101101" ;
   when "0110" =>  led7s <= "1111101" ;
   when "0111" =>  led7s <= "0000111" ;
   when "1000" =>  led7s <= "1111111" ;
   when "1001" =>  led7s <= "1101111" ;
   when others => led7s <= "0000000" ;
              end case;
              end process;
              end;
扩展后的程序
主控器程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kuozkq is
port(

   clk:in std_logic;
              rest:in std_logic;
              elect:out integer range 0 to 8;
              rea7A:out integer range 0 to 100;
              rea7B:out integer range 0 to 100
);
end;
architecture bhv of kuozkq is
begin
process(clk,rest)
variable tep:integer range 0 to 100;
begin
if rest='1' then tep:=100;elect<=0;
else
if clk'event and clk='0' then
if tep>90 then elect<=1;rea7A<=tep-90;rea7B<=tep-50;tep:=tep-1;
elsif tep>80 then elect<=2;rea7A<=tep-80;rea7B<=tep-50;tep:=tep-1;
elsif tep>55 then elect<=3;rea7A<=tep-55;rea7B<=tep-50;tep:=tep-1;
elsif tep>50 then elect<=4;rea7A<=tep-50;rea7B<=tep-50;tep:=tep-1;
elsif tep>40 then elect<=5;rea7A<=tep;rea7B<=tep-40;tep:=tep-1;
elsif tep>30 then elect<=6;rea7A<=tep;rea7B<=tep-30;tep:=tep-1;
elsif tep>5 then elect<=7;rea7A<=tep;rea7B<=tep-5;tep:=tep-1;
elsif tep>0 then elect<=8;rea7A<=tep;rea7B<=tep;tep:=tep-1;
else elect<=8;rea7A<=tep;rea7B<=tep;tep:=100;
end if;
end if;
end if;
end process;
end bhv;
LED控制程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kuoled is
port(
clk10:in std_logic;
elect:in integer range 0 to 8;
redA,greenA,yellowA,rightA,leftA:out std_logic;
redB,greenB,yellowB,rightB,leftB:out std_logic
);
end;
architecture bhv of kuoled  is
begin
process(clk10,elect)
begin
case elect is
when 0 => redA<='1';greenA<='0';yellowA<='0';rightA<='0';leftA<='0';redB<='1';greenB<='0';yellowB<='0';rightB<='0';leftB<='0';
when 1 => redA<='0';greenA<='0';yellowA<='0';rightA<='1';leftA<='0';redB<='1';greenB<='0';yellowB<='0';rightB<='0';leftB<='0';
when 2 => redA<='0';greenA<='0';yellowA<='0';rightA<='0';leftA<='1';redB<='1';greenB<='0';yellowB<='0';rightB<='0';leftB<='0';
when 3 => redA<='0';greenA<='1';yellowA<='0';rightA<='0';leftA<='0';redB<='1';greenB<='0';yellowB<='0';rightB<='0';leftB<='0';
when 4 => redA<='0';greenA<='0';yellowA<=clk10;rightA<='0';leftA<='0';redB<='1';greenB<='0';yellowB<='0';rightB<='0';leftB<='0';
when 5 => redA<='1';greenA<='0';yellowA<='0';rightA<='0';leftA<='0';redB<='0';greenB<='0';yellowB<='0';rightB<='1';leftB<='0';
when 6 => redA<='1';greenA<='0';yellowA<='0';rightA<='0';leftA<='0';redB<='0';greenB<='0';yellowB<='0';rightB<='0';leftB<='1';
when 7 => redA<='1';greenA<='0';yellowA<='0';rightA<='0';leftA<='0';redB<='0';greenB<='1';yellowB<='0';rightB<='0';leftB<='0';
when 8 => redA<='1';greenA<='0';yellowA<='0';rightA<='0';leftA<='0';redB<='0';greenB<='0';yellowB<=clk10;rightB<='0';leftB<='0';
when others =>null;
end case;
end process;
end;
扩展的显示程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY xianshi1 IS
PORT
(CLOCK:IN STD_LOGIC;
NUMIN:IN INTEGER RANGE 0 TO 99;
NUMA,NUMB:OUT INTEGER RANGE 0 TO 9
);
END;
ARCHITECTURE bhv OF xianshi1 IS
BEGIN
   PROCESS(CLOCK)
   BEGIN
     IF RISING_EDGE(CLOCK) THEN
               
       IF NUMIN>=10 THEN
         NUMA<=NUMIN/10;
         NUMB<=(NUMIN)rem(10);
                           
       ELSE
                               NUMA<=0;
                                          NUMB<=NUMIN;
       END IF;
     END IF;
   END PROCESS;
END;

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基于FPGA的交通灯设计.doc (2.37 MB, 下载次数: 63)

2020-11-16 20:07 上传

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