各位大神,我新学了几天 Verilog HDL 语言,写了个小小程序,使用高云芯片 GW1NS-4,运行后,不知什麽原因总是复位重启,能否各位指点下,感激不尽,目的是对输入的BCD码解码显示,led_dp 是小数点,led_en是外部MCU锁存信号, 我的思路是 用芯片的OSC 作为时钟,然后上电后,检测到 led_en 为高电平,才开始程序的运行,有22个LED的输出,有两个LED作小数点,程序中将这两点熄灭,其他的拼成七段数码显示,运行后,一段时间正常工作后,会不正常闪烁,然后回到上电后的状态,全亮
module ledigital(
// clk,
// rst_n,
led_dp,
led_en,
bcd_code,
led
);
//=================================================================
// PORT DECLARATION
//=================================================================
//input clk;
//input rst_n;
input led_dp;
input led_en;
input[3:0] bcd_code;
output[21:0] led;
//------------------------------------------------------------------
//
reg[19:0] timecnt;
reg[19:0] temp_led;
assign {led[21:15],led[13:9],led[7:0]} = {temp_led[19:0]};
wire osc_clk;
wire led_8pin;
wire led_14pin;
assign led[8]=led_8pin;
assign led[14]=led_14pin;
assign led_8pin = 1; // 熄灭小数点
assign led_14pin = 1;
reg[19:0] rst_count;
reg rst_en;
reg[3:0] temp_bcd;
reg temp_dp;
//reg temp_en;
reg[1:0] temp_work;
Gowin_OSC Gowin_OSC_inst ( // 用内部振荡作CLK
.oscout(osc_clk),
.oscen(1'd1)
);
always @(posedge osc_clk) begin
if(!rst_en)
begin
rst_count <= rst_count + 1'd1;
if(rst_count >= 20'b1111_1111_1111_1111_1110) //上电延时一段时间后,检测外部 led_en 是否拉高,拉高,则开始工作
begin
rst_count <= 0;
if(led_en)
rst_en <= 1;
end
end
end
always @(posedge osc_clk ) begin
if(!rst_en)
begin
temp_led <= 20'b0000_0000_0000_0000_0000;
end
else
begin
if(temp_work == 0) //因为 led_en 是锁存信号, 下降沿改变数据, 上升沿锁存
begin
if(!led_en) //检测下降沿
temp_work <= 1;
end
else if(temp_work == 1) //检测上升沿
begin
if(led_en)
begin
temp_bcd <= #20 bcd_code; //显示解码的BCD数据
case (temp_bcd)
5'd0: temp_led <= 20'b0101_1100_1100_0000_0000;
5'd1: temp_led <= 20'b0001_1101_0101_1011_1111;
5'd2: temp_led <= 20'b1100_0001_0011_1100_0000;
5'd3: temp_led <= 20'b0100_0001_1001_1110_0010;
5'd4: temp_led <= 20'b0000_0100_0000_0011_1111;
5'd5: temp_led <= 20'b0010_0010_1000_0110_0010;
5'd6: temp_led <= 20'b0111_0110_1000_0100_0000;
5'd7: temp_led <= 20'b0000_1101_0101_1011_0011;
5'd8: temp_led <= 20'b0101_0101_1000_0100_0000;
5'd9: temp_led <= 20'b0101_0101_1000_0110_0010;
5'd10: temp_led <= 20'b0101_0000_0000_0001_0001;
5'd11: temp_led <= 20'b0100_0000_1000_0000_0000;
5'd12: temp_led <= 20'b1011_1110_0110_0100_0000;
5'd13: temp_led <= 20'b0100_1000_1100_0000_0000;
5'd14: temp_led <= 20'b1010_0010_0010_0100_0000;
5'd15: temp_led <= 20'b1010_0010_1010_0101_0001;
default:temp_led <= 20'b1111_1111_1111_1111_1111;
endcase
temp_work<= 0;
end
end
end
end
endmodule
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