1.针对开发板晶振频率分频1H在脉冲
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity pinlv1Hz is
Port(clk:in std_logic;
CP:OUT std_logic);
end;
Architecture dd of pinlv1Hz is
signal q:std_logic_vector(24 downto 0);
SIGNAL C:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then q<=q+1;
if q=9999999 then q<="0000000000000000000000000";C<=not C;
end if;
end if;
end process;
CP<=C;
end;
综合无误后点file--creat/Update/Creat Symbol files for current file生成元件符号
2.编辑60s计数器
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity court60 is
Port(clk:in std_logic;
q:out std_logic_vector(6 downto 0));
end;
Architecture dd of court60 is
signal qq:std_logic_vector(6 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then qq<=qq+1;
if qq=59 then qq<="0000000";
end if;
end if;
end process;
q<=qq;
end;
综合无误后点file--creat/Update/Creat Symbol files for current file生成元件符号
3。创造一个除法器宏模块
创造一个除法器宏模块完成60进制分各位十进制，是为6进制
4。编辑一个6位宽和四位宽总线变两个4单根线的程序输出程序
Library ieee;
Use ieee.std_logic_1164.all;
entity zx64 is
Port(q:in std_logic_vector(6 downto 0);
qq:in std_logic_vector(3 downto 0);
x0,x1,x2,x3:buffer std_logic;
y0,y1,y2,y3:out std_logic);
end;
Architecture dd of zx64 is
begin
y0<=q(0);
y1<=q(1);
y2<=q(2);
y3<=q(3);
x0<=qq(0);
x1<=qq(1);
x2<=qq(2);
x3<=qq(3);
end;
综合无误后点file--creat/Update/Creat Symbol files for current file生成元件符号
5.便两位分时现实程序
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity fenshi is
Port(clk,a0,a1,a2,a3,b0,b1,b2,b3:in std_logic;
y0,y1,y2,y3,w0,w1:out std_logic);
end;
Architecture dd of fenshi is
signal q:std_logic_vector(7 downto 0);
begin
process(clk,a0,a1,a2,a3,b0,b1,b2,b3)
begin
if clk'event and clk='1' then q<=q+1;
if q<128 then
y0<=a0;y1<=a1;y2<=a2;y3<=a3;w0<='0';w1<='1';
else
y0<=b0;y1<=b1;y2<=b2;y3<=b3;w0<='1';w1<='0';
end if;
end if;
end process;
end;
综合无误后点file--creat/Update/Creat Symbol files for current file生成元件符号
6。编写一个7段显示码程序显示二进制位10进制
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity diaplay is
Port(q0,q1,q2,q3:in std_logic;
y6,y5,y4,y3,y2,y1,y0:out std_logic);
end;
Architecture dzb of diaplay is
signal qq:std_logic_vector(3 downto 0);
signal Q: std_logic_vector(6 downto 0);
begin
qq<=q3&q2&q1&q0;
----------------------------
process(qq)
begin
case qq is
when "0000"=>Q<="0000001"; --段码显示开发板共阳极，所以0显示，1不显示。
when "0001"=>Q<="1001111" ;
when "0010"=>Q<="0010010" ;
when "0011"=>Q<="0000110" ;
when "0100"=>Q<="1001100" ;
when "0101"=>Q<="0100100" ;
when "0110"=>Q<="0100000" ;
when "0111"=>Q<="0001111" ;
when "1000"=>Q<="0000000" ;
when "1001"=>Q<="0000100" ;
when others=>null;
end case;
end process;
y6<=q(6);y5<=q(5);y4<=q(4);y3<=q(3);y2<=q(2);y1<=q(1);y0<=q(0);
end;
综合无误后点file--creat/Update/Creat Symbol files for current file生成元件符号。
注意：以上编写如果用两位直接组合成四位二进制计数器，则无需用除法器。其他模块也根据个人习惯可以不同。
7.建立原理图文件
画图链接电路，在综合无误后，与开发板管脚对应相连，再综合无误后即可仿真。
注意：硬件仿真时，对于不用的管脚要设置成三态输出。
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