算数运算时FPGA编程设计中常会用到的功能,其规则直接影响变成效果,调用use ieee.std_logic_unsigned.all;此程序包对不同的数据类型可以进行适当的算数运算: 1.对std_logic_vector()可进行相同位数的加减运算(被加数必须和输出位数相同); 2.对std_logic_vector()可进行相乘法运算(积的位数等于俩乘数位数之和);
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity adder_n is
port(a,b:in std_logic_vector(4 downto 0);
c:in std_logic_vector(2 downto 0);
Sum1,sum2:out std_logic_vector(9 downto 0);
sum4,sum3 :out std_logic_vector(4 downto 0) );
end;
Architecture add of adder_n is
begin
Sum1<="00000"&a + b;
Sum2<=a * b;
sum3<=a - b;
sum4<=a + b;
end;
3.对Integer(整数)可以进行加、减、乘、除和取余运算; Library ieee; Useieee.std_logic_1164.all; Useieee.std_logic_unsigned.all; entity adder_n is generic(n:integer:=4);----改变w的值可以改变运算宽度 port(a:in integerrange 0 to 4095; dd,b:in integer range 0 to 255; cin:in integer range 0 to 64; Sum1,sum2:out integer range 0 to 4095; ddd:out integer range 0 to 1023; co1,co2:out integer range 0 to 1023); end; Architecture add of adder_n is begin Sum1<=a * b;---a,b一个可以是常数,如 Sum1<=2 * b sum2<=a + b; ddd<=a / b;---- 虽然是除,但实际为商 取整运算 co1<=a - dd; co2<= a REM cin; --- 取余 end; |