modulecnt_dec7s(clk,clrn,ena,q,cout);
inputclk,clrn,ena;
output[15:0] q;
output cout;
wire x1,x2,x3;
cnt4eu1(.q(x1),.cout(x2),.clk(clk),.clrn(clrn),.ena(ena));
cnt4eu2(.q(x3),.cout(cout),.clk(clk),.clrn(clrn),.ena(x2));
dec7su3(.a(x1),.q(q[7:0]));
dec7su4(.a(x3),.q(q[15:8]));
endmodule
module cnt4e(clk,clrn,ena,cout,q);
inputclk,clrn,ena;
output reg[3:0] q;
output reg cout;
always @(negedgeclrn or posedge clk)
begin
if (~clrn) q=0;
else begin
if (ena) q=q+1;
if(q==9) cout=1;
else cout=0;end
end
endmodule
module dec7s(a,q);
input [3:0] a;
output reg[7:0] q;
always @(a)
begin
case(a)
0:q='b00111111;1:q='b00000110;
2:q='b01011011;3:q='b01001111;
4:q='b01100110;5:q='b01100101;
6:q='b01111101;7:q='b00000111;
8:q='b01111111;9:q='b01101111;
10:q='b01110111;11:q='b01111110;
12:q='b00111001;13:q='b01011110;
14:q='b01111001;15:q='b01110001;
endcase
end
endmodule
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