`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:59:46 10/30/2017
// Design Name:
// Module Name: filterhd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module filterhd(
input clk, //fpga clock
output [15:0] dadata, //DA data
output adclk,
output daclk,
input [7:0] addata,
input rest //A
);
wire [7:0] addata;
reg [15:0] middata;
reg [7:0] ad_rom[9:0];
reg [15:0] da;
reg[7:0] dadata;
reg [3:0] m;
wire clk_25;
assign adclk=clk_25;
assign daclk=clk_25;
always@( posedge clk_25) begin
if (m==10)begin
m<=0;
end
ad_rom[m]<=addata;
m<=m+1;
end
always@(posedge clk_25)begin
middata<=ad_rom[0]+ad_rom[1]+ad_rom[2]+ad_rom[3]+ad_rom[4]+ad_rom[5]+ad_rom[6]+ad_rom[7]+ad_rom[8]+ad_rom[9];
da<=middata/10;
dadata=da[7:0];
end
PLL PLL_inst
(// Clock in ports
.CLK_IN1(clk), // IN
// Clock out ports
.CLK_OUT1(clk_50), // OUT
.CLK_OUT2(clk_25), // OUT
// Status and control signals
.RESET(1'b0),// IN
.LOCKED()); // OUT
wire [35:0] CONTROL0;
wire [255:0] TRIG0;
chipscope_icon icon_debug (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila ila_filter_debug (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
// .CLK(dma_clk), // IN
.CLK(clk_25), // IN
.TRIG0(TRIG0) // IN BUS [255:0]
//.TRIG_OUT(TRIG_OUT0)
);
assign TRIG0[7:0]=addata;
assign TRIG0[23:8]=middata;
assign TRIG0[39:24]=da;
assign TRIG0[47:40]=dadata;
endmodule |
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