用Verilog来实现d触发器2分频的Verilog hdl程序:
module dff_2(clk,rst,clk_out);
input clk,rst;
output clk_out;
wire clk,rst;
reg clk_out;
always @(posedge clk or negedge rst)
if(!rst)
begin
clk_out<=0;
end
else
begin
clk_out<=~clk_out;
end
endmodule
通过RTL viewer 得到的原理图;
仿真图如图示: