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- module main(
- input clk, //50Mhz 时钟输入
- output reg [7:0] seg_code, //数码管段码 8位 A~DP
- output reg [3:0] bit_code //数码管位码 4位 ~1:千位 ~2:百位 ~4:十位 ~8:个位
- );
- function [7:0] display; //16进制数码管段码查询
- input [3:0] hex;
- begin
- case(hex)
- 4'h0:display = 8'h3F;
- 4'h1:display = 8'h06;
- 4'h2:display = 8'h5B;
- 4'h3:display = 8'h4F;
- 4'h4:display = 8'h66;
- 4'h5:display = 8'h6D;
- 4'h6:display = 8'h7D;
- 4'h7:display = 8'h07;
- 4'h8:display = 8'h7F;
- 4'h9:display = 8'h6F;
- 4'hA:display = 8'h77;
- 4'hB:display = 8'h7C;
- 4'hC:display = 8'h39;
- 4'hD:display = 8'h5E;
- 4'hE:display = 8'h79;
- 4'hF:display = 8'h71;
- endcase
- end
- endfunction
- reg [15:0] hex = 0; //数码管通过16进制显示出此寄存器的值
- reg [15:0] i = 0;
- reg [1:0] j = 0;
- reg [31:0] k = 0;
- always @(posedge clk) begin //CLK上升沿触发
- //数码管动态扫描 (FPGA的段码和位码可以并行发送 所以不需要消影)
- i = i + 1'd1;
- if(i == 16'd50000) begin //50000个时钟即为1ms
- i = 0;
- j <= j + 1'd1;
- //共阴或共阳 如果显示不正确 可将 seg_code 或 bit_code 前的 ~号去除 并检查A~DP的Pin是否设置颠倒
- case(j)
- 2'd0:seg_code <= ~display(hex[15:12]);
- 2'd1:seg_code <= ~display(hex[11:8]);
- 2'd2:seg_code <= ~display(hex[7:4]);
- 2'd3:seg_code <= ~display(hex[3:0]);
- endcase
- bit_code <= ~(1'd1 << j);
- end
- //16进制累加 1秒+1
- k = k + 1'd1;
- if(k == 50000000) begin
- k = 1'd0;
- hex <= hex + 1'd1;
- end
- end
- endmodule
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