接上篇：http://www.51hei.com/bbs/dpj-28500-1.html
五、八位二进制数减法器
一）、不带符号
该减法器只能大数减小数，不带正负号，且运算在时钟脉冲上升沿到来时进行计算。
Library ieee;
Use ieee.std_logic_1164.all;
Entity jianfaqi8 is
Port(a,b:in std_logic_vector(7 downto 0);
CLK:in std_logic;
S:out std_logic_vector(7 downto 0);
co:out std_logic);
end jianfaqi8;
Architecture add of jianfaqi8 is
signal a1,b1:std_logic_vector(7 downto 0);
component adder8 is
Port(a,b:in std_logic_vector(7 downto 0);
cin:in std_logic;
S:out std_logic_vector(7 downto 0);
co:out std_logic);
end component;
begin
process(a,b,CLK)
begin
if CLK'event and CLK='1' then
a1<=a;
b1<=b;
end if;
end process;
U:adder8 port map(a1,(not b1),'1',S,co);
end;
二）带符号
可以大减小，也可小减大，输出正负的计算结果
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity jianfaqi8 is
Port(a,b:in std_logic_vector(7 downto 0);
CLK:in std_logic;
S:out std_logic_vector(7 downto 0);
co:out std_logic);
end jianfaqi8;
Architecture add of jianfaqi8 is
signal a1,b1,S1,S2,S3:std_logic_vector(7 downto 0);
signal c1,c2:std_logic;
component adder8 is
Port(a,b:in std_logic_vector(7 downto 0);
cin:in std_logic;
S:out std_logic_vector(7 downto 0);
co:out std_logic);
end component;
begin
process(a,b,CLK)
begin
if CLK'event and CLK='1' then
a1<=a;b1<=b;
end if;
end process;
U:adder8 port map(a1,(not b1),'1',S1,c1);
c2<=c1 xor '1';
co<=c2;
Process(S1,c1)
begin
if c2='0' then
S<=S1;
else
S2<= S1-1;
S<=not S2;
end if;
end process;
end;
|
