74LS161十进制计数器的VHDL程序

先编辑一个74LS161十进制计数器的vhdl程序：
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity court161 is                                   
 port( clk,CTT,CTP,LD,CR:in std_logic;
               D3,D2,D1,D0: in  std_logic;               
               Q:out std_logic_VECTOR(3 DOWNTO 0); 
               Co: out std_logic);
end court161;                                        
architecture court of court161 is                       
 signal a,b,c:  std_logic  ;
 signal D,CQI:std_logic_vector(3 downto 0);                       
 begin
   D<=D3&D2&D1&D0;
   a<=CTT and CTP;
   b<=(not (CQI(3) and CQI(0)))and LD;                                     
   process(clk,CTT,CTP,LD,CR,D3,D2,D1,D0)                                     
      begin                                     
      if a='1' then
         if  clk'event and clk='1' then
             if b='0' then CQI<=D;           
              else   CQI<=CQI+1;              
              end if;                             
         end if;
         if CQI=9 then c<='1';                      
          else c<='0';                            
          end if;
       end if;
     if clk'event and clk='1' then Co<=c;
     end if;                                    
     if CR='0' then CQI<="0000";
     end if;
       Q<=CQI ;                               
      end process;                                                          
end ;   

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