vhdl驱动lcd解决了ISE联合modelsim仿真看不见波形的问题

ID:80436 · 发表于 2015-5-19 23:06

本帖最后由 liuqq 于 2015-5-19 23:07 编辑

搞一个月解决了ISE联合modelsim仿真看不见波形的问题，写了一整天代码，最后结果还是有点问题，明天找老师帮忙吧~

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library
declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LCDb is
Port ( clk : in STD_LOGIC;--48MHZ
reset : in STD_LOGIC;
display : in STD_LOGIC;
xck : out STD_LOGIC;--6MHz
din : in STD_LOGIC_VECTOR(2 downto 0);
dout : out STD_LOGIC_VECTOR(7
downto 0));
end LCDb;
architecture LCDb_arch of LCDb is
signal sram1 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";--数据寄存器
signal sram2 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal sram3 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal sram4 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal sram5 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal sram6 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal sram7 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal sram8 :std_LOGIC_VECTOR(8 downto 0)
:="000000000";
signal a : STD_LOGIC :='0';--系??分频用
signal b : integer range 0 to 3;--系统分频用clk八分频得到xck
signal c : integer range 0 to 72;--寄存器数据写入计数
signal d : integer range 0 to 9;--寄存器数据读出计数
begin
xck<=a;
process(clk)
variable a_a :integer range 0 to 3;
begin
if(reset='1') then
if(clk'event and clk='0') then
if(a_a=3) then
a_a:=0;
a<=not a;
else
a_a:=a_a+1;
end
if;
end if;
end if;
end process;
process(clk)
begin
if(display='1') then
if(clk'event and clk='0') then
if(c=72) then
c<=0;
c<=c+1;
else
if(c=2) then
sram1(8 downto 6)<=din;
c<=c+1;
elsif(c=5) then
c<=c+1;
sram1(5 downto 3)<=din;
elsif(c=8) then
sram1(2 downto 0)<=din;
c<=c+1;
elsif(c=11) then
sram2(8 downto 6)<=din;
c<=c+1;
elsif(c=14) then
sram2(5 downto 3)<=din;
c<=c+1;
elsif(c=17) then
sram2(2 downto 0)<=din;
c<=c+1;
elsif(c=20) then
sram3(8 downto 6)<=din;
c<=c+1;
elsif(c=23) then
sram3(5 downto 3)<=din;
c<=c+1;
elsif(c=26) then
sram3(2 downto 0)<=din;
c<=c+1;
elsif(c=29) then
sram4(8 downto 6)<=din;
c<=c+1;
elsif(c=32) then
sram4(5 downto 3)<=din;
c<=c+1;
elsif(c=35) then
sram4(2 downto 0)<=din;
c<=c+1;
elsif(c=38) then
sram5(8 downto 6)<=din;
c<=c+1;
elsif(c=41) then
sram5(5 downto 3)<=din;
c<=c+1;
elsif(c=44) then
sram5(2 downto 0)<=din;
c<=c+1;
elsif(c=47) then
sram6(8 downto 6)<=din;
c<=c+1;
elsif(c=50) then
sram6(5 downto 3)<=din;
c<=c+1;
elsif(c=53) then
sram6(2 downto 0)<=din;
c<=c+1;
elsif(c=56) then
sram7(8 downto 6)<=din;
c<=c+1;
elsif(c=59) then
sram7(5 downto 3)<=din;
c<=c+1;
elsif(c=62) then
sram7(2 downto 0)<=din;
c<=c+1;
elsif(c=65) then
sram8(8 downto 6)<=din;
c<=c+1;
elsif(c=68) then
sram8(5 downto 3)<=din;
c<=c+1;
elsif(c=71) then
sram8(2 downto 0)<=din;
c<=c+1;
else
c<=c+1;
end if;
end
if;
end if;
end if;
end process;
process(a)
begin
if(display='1') then
if(a'event and a='0') then
if(d=9) then
dout<=sram1(8 downto 1);
d<=0;
d<=d+1;
else
if(d=0) then
dout<=sram1(8 downto 1);
elsif(d=1) then
dout(7)<=sram1(0);
dout(6 downto 0)<=sram2(8 downto 2);
elsif(d=2) then
dout(7 downto 6)<=sram2(1 downto 0);
dout(5 downto 0)<=sram3(8 downto 3);
elsif(d=3) then
dout(7 downto 5)<=sram3(2 downto 0);
dout(4 downto 0)<=sram4(8 downto 4);
elsif(d=4) then
dout(7 downto 4)<=sram4(3 downto 0);
dout(3 downto 0)<=sram5(8 downto 5);
elsif(d=5) then
dout(7 downto 3)<=sram5(4 downto 0);
dout(2 downto 0)<=sram6(8 downto 6);
elsif(d=6) then
dout(7 downto 2)<=sram6(5 downto 0);
dout(1 downto 0)<=sram7(8 downto 7);
elsif(d=7) then
dout(7 downto 1)<=sram7(6 downto 0);
dout(0)<=sram8(8);
else
dout<=sram8(7 downto 0);
end if;
d<=d+1;
end
if;
end if;
end if;
end process;
end LCDb_arch;

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vhdl驱动lcd解决了ISE联合modelsim仿真看不见波形的问题

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