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1、Error: Can't continue timing simulation because delay annotation information for design is missing
这是因为未对工程进行综合编译，无法仿真。
解决办法：编译一次
2、Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
CLK没有定义成时钟信号
解决办法：pin lanner中将clk定义到晶振引脚或clk接到某个时钟信号（可以使pll输出）上
3、Warning: Converted tri-state buffer "init_module:j2|initial_control_module:u1|wr_data[0]" feeding internal logic into a wire
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