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——24进制计数器（数码管显示）用VHDl编写 ——楼主用实验板验证过满足计数０～２３ 顶层文件 led_24 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity led_24 is port(clk,clr,ena:in std_logic; cq10_out,cq2_out:out std_logic_vector(3 downto 0) ); end led_24;
architecture behav of led_24 is component led24 port(clk,clr,ena:in std_logic; cnt10,cnt2:out std_logic_vector(3 downto 0)); end component;
component decoder_10 port(cq10_1:IN STD_LOGIC_VECTOR (3 DOWNTO 0); cq10_out:OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); end component;
component decoder_2 PORT (cq2_1:IN STD_LOGIC_VECTOR (3 DOWNTO 0); cq2_out:OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); end component;
signal net1, net2 :std_logic_vector(3 downto 0); begin u1 : led24 port map(clk=>clk,clr=>clr,ena=>ena,cnt10=>net1,cnt2=>net2); u2 : decoder_10 port map(cq10_1=>net1,cq10_out=>cq10_out); u3 : decoder_2 port map(cq2_1=>net2,cq2_out=>cq2_out);
END architecture behav;
——例化元器件 U1： ——24进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity led24 is port(clk,clr,ena:in std_logic; cnt10,cnt2:out std_logic_vector(3 downto 0) );
end led24 ; architecture behav of led24 is
begin
process(clk,clr,ena) variable cq2:std_logic_vector(3 downto 0); variable cq10:std_logic_vector(3 downto 0); begin if clr='1' then cq2:="0000"; cq10:="0000"; elsif clk'event and clk='0' then if ena='1' then if cq10="1001" then cq10:="0000"; cq2:=cq2+'1'; else cq10:=cq10+'1'; end if; if cq2="0010" and cq10="0100" then cq2:="0000";cq10:="0000"; end if; end if; end if; cnt2<=cq2; cnt10<=cq10; end process ; end architecture behav;
——例化元器件u2 ——个位数译码电路 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_10 IS PORT (cq10_1:IN STD_LOGIC_VECTOR (3 DOWNTO 0); cq10_out:OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END;
ARCHITECTURE ONE OF decoder_10 IS BEGIN PROCESS (cq10_1) BEGIN CASE cq10_1 IS WHEN "0000" => cq10_out<= "1000000"; WHEN "0001" => cq10_out<= "1111001"; WHEN "0010" => cq10_out<= "0100100"; WHEN "0011" => cq10_out<= "0110000"; WHEN "0100" => cq10_out<= "0011001"; WHEN "0101" => cq10_out<= "0010010"; WHEN "0110" => cq10_out<= "0000010"; WHEN "0111" => cq10_out<= "1111000"; WHEN "1000" => cq10_out<= "0000000"; WHEN "1001" => cq10_out<= "0010000"; WHEN OTHERS => cq10_out<= "1111111"; END CASE; END PROCESS; END architecture ONE;
—— 例化元器件u3 十位数译码电路
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_2 IS PORT (cq2_1:IN STD_LOGIC_VECTOR (3 DOWNTO 0); cq2_out:OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END;
ARCHITECTURE two OF decoder_2 IS BEGIN PROCESS (cq2_1) BEGIN CASE cq2_1 IS WHEN "0000" => cq2_out<= "1000000"; WHEN "0001" => cq2_out<= "1111001"; WHEN "0010" => cq2_out<= "0100100"; WHEN OTHERS => cq2_out<= "1111111"; END CASE; END PROCESS; END architecture two; 波形见附件
ＲＴＬ图
file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\wps7658.tmp.jpg 计数器波形
译码之后波形 file:///C:\Users\ADMINI~1\AppData\Local\Temp\ksohtml\wps7669.tmp.jpg
——这里有完整的工程
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